From patchwork Thu Jul 13 09:42:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 9838089 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C9DF6602D8 for ; Thu, 13 Jul 2017 09:42:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B7EA92854F for ; Thu, 13 Jul 2017 09:42:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A9EA6286A3; Thu, 13 Jul 2017 09:42:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C6DA02854F for ; Thu, 13 Jul 2017 09:42:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750949AbdGMJmX (ORCPT ); Thu, 13 Jul 2017 05:42:23 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:34647 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750877AbdGMJmW (ORCPT ); Thu, 13 Jul 2017 05:42:22 -0400 Received: by mail-wm0-f66.google.com with SMTP id p204so3906066wmg.1 for ; Thu, 13 Jul 2017 02:42:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=luDcng8qYM3PcFE0gFZG9bJcDruK+UoJXQl6iRZFk1Q=; b=iAkDoJmai3VhPgFZh2Tdm+axrbfGzESX3GdvNqXF5OjXSXXTY02CNXgoftcqoMm7FA i3wP0kdrLF54JQRLy+PAOOUIR/eg7MSaxggc0D9X4vAF1JZ37pR0rByiFZUbofVltmQt NTA+iDuAciyVkbiRUw2Cuo/1PEIFuD8a03BP2RFhk+whshPeOAZJR+cCsn2OF0aAMxGY XHSxMwk71g56zLyh7om7sUXPozxDuWcxWz6mSIoJIjKU6Nw2Pva95z2aTL2/TExSI6R3 f/GR/fEXvTbORY2lArXfYYQkQ7UuPi/E1J8e4bb+BWPcqDSNz6tzL2H6f153yTYi3tLz j9QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=luDcng8qYM3PcFE0gFZG9bJcDruK+UoJXQl6iRZFk1Q=; b=Yx7iTJy3n301nF0fYb/3v9D1UCoHxcqSiGYWEiEGQA+zf1NGyKBhxUqvwik22Roa6L /MWNo9WTQ6QbI4u21gu3vVl40bAsHzkc4r3a5+RUxhkbR5WSTY4Jg9qk3qHO5R58kUHw twzAwqJ/L8Rop1dmgKRxOoW06wAsLmIogNsRHMgcdCdi3eQSRyfoLVOvptOOgFDeCygB 3V1dBjHRCM/LSBVWghPe57+QpcH9nPklJlA8cQlFZ3kPHhDUk+ONtbALWV9PM+dLaEW0 Qxk9jBhhNRRezroexkLDnmnEHF6/pq0Pxue6MXAoVOZpq+P00HsHi/wilLrAL8dCnDQ5 9EHg== X-Gm-Message-State: AIVw113UUB9qrHRBtL6wsV0R1sIdIq1avDMsUQyC/RD1uKljWDdxTDBg mv2FZzQV3sGX3Q== X-Received: by 10.28.178.69 with SMTP id b66mr1208954wmf.99.1499938941360; Thu, 13 Jul 2017 02:42:21 -0700 (PDT) Received: from mephisto.homenet.telecomitalia.it (host157-150-dynamic.54-79-r.retail.telecomitalia.it. [79.54.150.157]) by smtp.gmail.com with ESMTPSA id x98sm4663724wrb.47.2017.07.13.02.42.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 02:42:20 -0700 (PDT) From: Carlo Caione To: mturquette@baylibre.com, linux-clk@vger.kernel.org, dvhart@infradead.org, pierre-louis.bossart@linux.intel.com, sboyd@codeaurora.org, linux@endlessm.com, eballetbo@gmail.com, andriy.shevchenko@linux.intel.com Cc: Carlo Caione Subject: [PATCH v2] clk: x86: Do not gate clocks enabled by the firmware Date: Thu, 13 Jul 2017 11:42:13 +0200 Message-Id: <20170713094213.2775-1-carlo@caione.org> X-Mailer: git-send-email 2.13.2 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra Signed-off-by: Carlo Caione Acked-by: Andy Shevchenko Acked-by: Darren Hart (VMware) --- drivers/clk/x86/clk-pmc-atom.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/x86/clk-pmc-atom.c b/drivers/clk/x86/clk-pmc-atom.c index 2b60577703ef..3c73d2e564ca 100644 --- a/drivers/clk/x86/clk-pmc-atom.c +++ b/drivers/clk/x86/clk-pmc-atom.c @@ -185,6 +185,13 @@ static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id, pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; spin_lock_init(&pclk->lock); + /* + * If the clock was already enabled by the firmware mark is a critical + * to avoid it being gated by the clock framework if no driver owns it + */ + if (plt_clk_is_enabled(&pclk->hw)) + init.flags |= CLK_IS_CRITICAL; + ret = devm_clk_hw_register(&pdev->dev, &pclk->hw); if (ret) { pclk = ERR_PTR(ret);