diff mbox

[3/4] clk: sunxi-ng: Make fractional helper less chatty

Message ID 20170730164150.26302-4-jernej.skrabec@siol.net (mailing list archive)
State Awaiting Upstream
Headers show

Commit Message

Jernej Škrabec July 30, 2017, 4:41 p.m. UTC
ccu_frac_helper_read_rate() prints some info which is not really
helpful except during debugging.

Replace printk() with pr_debug().

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu_frac.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Chen-Yu Tsai July 31, 2017, 7:15 a.m. UTC | #1
()On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
<jernej.skrabec@siol.net> wrote:
> ccu_frac_helper_read_rate() prints some info which is not really
> helpful except during debugging.
>
> Replace printk() with pr_debug().
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>

Queued as a fix for 4.13 with the following tag:

Fixes: 89a3dfb78707 ("clk: sunxi-ng: Add fractional lib")

The rationale being the previous two patches actually enable
the ccu_frac_helper_read_rate() code path, and we don't want
the users to be annoyed by all the noise.

ChenYu
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diff mbox

Patch

diff --git a/drivers/clk/sunxi-ng/ccu_frac.c b/drivers/clk/sunxi-ng/ccu_frac.c
index 8b5eb7756bf7..ff9e72dc5337 100644
--- a/drivers/clk/sunxi-ng/ccu_frac.c
+++ b/drivers/clk/sunxi-ng/ccu_frac.c
@@ -67,18 +67,18 @@  unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
 {
 	u32 reg;
 
-	printk("%s: Read fractional\n", clk_hw_get_name(&common->hw));
+	pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw));
 
 	if (!(common->features & CCU_FEATURE_FRACTIONAL))
 		return 0;
 
-	printk("%s: clock is fractional (rates %lu and %lu)\n",
-	       clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
+	pr_debug("%s: clock is fractional (rates %lu and %lu)\n",
+		 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
 
 	reg = readl(common->base + common->reg);
 
-	printk("%s: clock reg is 0x%x (select is 0x%x)\n",
-	       clk_hw_get_name(&common->hw), reg, cf->select);
+	pr_debug("%s: clock reg is 0x%x (select is 0x%x)\n",
+		 clk_hw_get_name(&common->hw), reg, cf->select);
 
 	return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
 }