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Mon, 2 Oct 2017 10:48:24 +0000 (GMT) X-AuditID: cbfec7f4-f79ab6d000003290-23-59d2197930dc Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 70.7F.18832.87912D95; Mon, 2 Oct 2017 11:48:24 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OX600IRHZCIUD50@eusync3.samsung.com>; Mon, 02 Oct 2017 11:48:24 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 1/4] clk: samsung: Instantiate Exynos4412 ISP clocks only when available Date: Mon, 02 Oct 2017 12:47:56 +0200 Message-id: <20171002104759.25944-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171002104759.25944-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOIsWRmVeSWpSXmKPExsWy7djP87qVkpciDf5eYLXYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MVXu2MhXsU6zYeXkmYwPjLpkuRk4OCQETiZMTO5kgbDGJC/fWs4HYQgJL GSVm7g7vYuQCsj8zSuzafJwJpmHn0/msEEXLGCW2tEVBFDUwSTz59RkswSZgKNH1tgtskoiA g8TnT68ZQYqYBdqYJM4e2A82SVggSuJQz3NmEJtFQFVi76E2MJtXwFbi+qqfrBDb5CXeL7jP CGJzCthJNB9YyQIySEKgkU1i7aFnbBBFLhLbFr+HsoUlXh3fwg5hy0h0dhyEOrufUaKpVRvC nsEoce4tL4RtLXH4+EWwZcwCfBKTtk0HOoIDKM4r0dEmBFHiIfF/1jyoMY4S55YtY4f4fiKj xN65FRMYpRcwMqxiFEktLc5NTy020StOzC0uzUvXS87P3cQIjM7T/45/2cG4+JjVIUYBDkYl Hl4Nk4uRQqyJZcWVuYcYJTiYlUR4edkuRQrxpiRWVqUW5ccXleakFh9ilOZgURLntY1qixQS SE8sSc1OTS1ILYLJMnFwSjUwdtdGX6mYULdXKSdn84YP/QdeZmVMy/QP9Pj/yWX653llwvka W5qsP2jIR4p2s3bM29mwX0btdwb7qhm/eU+tKw8v2dHSfujm/siLs3f4dmkt++3BcXh1cZ1p epbK0r6CwovaCQt111q33JcTFlEPdnW9Up9UY6z0Z5rQ7oj4/fx8/1hj07cqsRRnJBpqMRcV JwIAWWLN7soCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplluLIzCtJLcpLzFFi42I5/e/4Vd0KyUuRBr/OqFlsnLGe1eL6l+es FpPuT2CxOH9+A7vFx557rBYzzu9jslh75C67xeE37awOHB6bVnWyefRtWcXo8XmTXABzFJdN SmpOZllqkb5dAlfGqj1bmQr2KVbsvDyTsYFxl0wXIyeHhICJxM6n81khbDGJC/fWs4HYQgJL GCXeXpODsJuYJC5/MAKx2QQMJbredoHViAg4SHz+9Jqxi5GLg1mgg0liz96HYAlhgSiJjvbp YENZBFQl9h5qYwaxeQVsJa6v+gm1TF7i/YL7jCA2p4CdRPOBlSwQy2wl5q7dzD6BkXcBI8Mq RpHU0uLc9NxiQ73ixNzi0rx0veT83E2MwEDaduzn5h2MlzYGH2IU4GBU4uHVMLkYKcSaWFZc mXuIUYKDWUmEl5ftUqQQb0piZVVqUX58UWlOavEhRmkOFiVx3t49qyOFBNITS1KzU1MLUotg skwcnFINjLOuS9kyybmk2V2JZHHtePF+1g5tlTWbPaYrCuXauccl1fz8tX6uT6Ti8TlBaSX2 nW/DZlz4n3I6euL2i1dcj3+cpSE9VeZGdNiPp/PMXl+prlXOfHxu3dS/Ny32WBXn7RVc4x91 VtVnm/AOrX858u0POHNC5+WyFF979ObtWrfSfVJMJXUquUosxRmJhlrMRcWJAGbIxaAgAgAA X-CMS-MailID: 20171002104824eucas1p1de6466888524f3f3f097086b1e2388ff X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20171002104824eucas1p1de6466888524f3f3f097086b1e2388ff X-RootMTR: 20171002104824eucas1p1de6466888524f3f3f097086b1e2388ff References: <20171002104759.25944-1-m.szyprowski@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some additional registers for the ISP (Camera subsystem) clocks are partially located in the SOC area, which belongs to ISP power domain. Istatiate those clocks only when provided clock registers resource covers those registers. This is a preparation for adding a separate clock driver for ISP clocks, which will be intergated with power domain using runtime PM feature. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..bdd68247e054 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -822,6 +822,12 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), + DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), + DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), + DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), +}; + +static struct samsung_div_clock exynos4x12_isp_div_clks[] = { DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, @@ -831,9 +837,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { 4, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3, CLK_GET_RATE_NOCACHE, 0), - DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), - DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), - DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), }; /* list of gate clocks supported in all exynos4 soc's */ @@ -1132,6 +1135,13 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 0, 0), GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 0, 0), + GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), + GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), + GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, + 0), +}; + +static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, @@ -1184,10 +1194,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), - GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), - GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, - 0), }; static const struct samsung_clock_alias exynos4_aliases[] __initconst = { @@ -1522,6 +1528,8 @@ static void __init exynos4_clk_init(struct device_node *np, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { + struct resource res; + samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); samsung_clk_register_div(ctx, exynos4x12_div_clks, @@ -1533,6 +1541,15 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_fixed_factor(ctx, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); + + of_address_to_resource(np, 0, &res); + if (resource_size(&res) > 0x18000) { + samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, + ARRAY_SIZE(exynos4x12_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, + ARRAY_SIZE(exynos4x12_isp_gate_clks)); + } + if (of_machine_is_compatible("samsung,exynos4412")) { exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,