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Tue, 3 Oct 2017 10:00:30 +0000 (GMT) X-AuditID: cbfec7f2-f793b6d000003243-bc-59d35fbe41e1 Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id BE.54.20118.DBF53D95; Tue, 3 Oct 2017 11:00:29 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OX8005VZRSOD560@eusync2.samsung.com>; Tue, 03 Oct 2017 11:00:29 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 3/9] clk: samsung: Remove double assignment to CLK_ARM_CLK id in Exynos4 driver Date: Tue, 03 Oct 2017 12:00:10 +0200 Message-id: <20171003100016.32029-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171003100016.32029-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEIsWRmVeSWpSXmKPExsWy7djPc7r74i9HGhy5b2yxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3eLwm3ZWB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoErY8eL20wFmzkrdn89z97A2MrRxcjJISFgIvGm7xk7hC0mceHeerYuRi4OIYGljBLf 3l9igXA+M0ocPLSAFaZj8/UPUIlljBLXv+1jhXAamCT2bVjOAlLFJmAo0fW2iw3EFhFwkPj8 6TUjSBGzwFNGiROHnjN1MXJwCAskSvRvFQCpYRFQlVhz7xxYPa+ArUTzw7dQN8lLvF9wnxHE 5hSwk1j8cTnYMgmBRjaJy/13WCCKXCT6bn+FOk9Y4tXxLVDNMhKXJ3dD1fQzSjS1akPYMxgl zr3lhbCtJQ4fvwjWyyzAJzFp23RmkNskBHglOtqEuhjZgUwPiQUyEMWOErM3t0K9O5FR4tKy j2wTGKUXMDKsYhRJLS3OTU8tNtYrTswtLs1L10vOz93ECIzJ0/+Of9rB+PWE1SFGAQ5GJR7e HR6XIoVYE8uKK3MPMUpwMCuJ8E7zuhwpxJuSWFmVWpQfX1Sak1p8iFGag0VJnNc2qi1SSCA9 sSQ1OzW1ILUIJsvEwSnVwFj/8Ndd/y0JXJqT9QyN/zsceL7z++LrZ1iuNd265PV1o9MrlknM CZkXSnzP9v6c9c84eO77wCUztxVr7w1NLWPJXLdxpf3JP4dWLPvUF+Fx4PL+6aIrjHpNupj/ rjONKLr4tS5A0mL2Ue+/MzQm1F/+oV+wNpXlX7eY6eLwDfOP6u2Lfyw67fsdJZbijERDLeai 4kQAmsK2d8UCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupiluLIzCtJLcpLzFFi42I5/e/4Fd298ZcjDV70mVtsnLGe1eL6l+es FufPb2C3+Nhzj9Vixvl9TBZrj9xltzj8pp3Vgd1j06pONo++LasYPT5vkgtgjuKySUnNySxL LdK3S+DK2PHiNlPBZs6K3V/PszcwtnJ0MXJySAiYSGy+/oEFwhaTuHBvPVsXIxeHkMASRolX x7azQzhNTBKrXhxnAqliEzCU6HrbxQZiiwg4SHz+9JoRpIhZ4CmjxPG3U8FGCQskSjzddIYd xGYRUJVYc+8cWAOvgK1E88O37BDr5CXeL7jPCGJzCthJLP64nBXEFgKqaZy/inkCI+8CRoZV jCKppcW56bnFRnrFibnFpXnpesn5uZsYgSG07djPLTsYu94FH2IU4GBU4uHd4XEpUog1say4 MvcQowQHs5II7zSvy5FCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeXv3rI4UEkhPLEnNTk0tSC2C yTJxcEo1MIo7e65t2rdrXk/RZ2OnOQ/W5rpMs1rtfuiekcaubK6KQMPI4wnhvHv0TyZ6tJ1c 9eUlO99unWeCwZkx88JPX5Ga/cTd2jzNTZn/fWm/68yrGjpr1ZbnN0x/4TK7eZON84tbaknR htbTzjlP36F6pMnii6dN1h/3aa9bV5tyBGzf0bIsa+KDDiWW4oxEQy3mouJEAHoioEEdAgAA X-CMS-MailID: 20171003100030eucas1p1a20ef57eada2009d1c83804b475fd1b6 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20171003100030eucas1p1a20ef57eada2009d1c83804b475fd1b6 X-RootMTR: 20171003100030eucas1p1a20ef57eada2009d1c83804b475fd1b6 References: <20171003100016.32029-1-m.szyprowski@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CLK_ARM_CLK ("armclk") clock is provided by cpu-clk subdriver, which is instantiated after creating all divider clocks from exynos4_div_clks array. There is no point assigning this id to "div_core2" clock and later overwrite with proper "armcpu" clock by cpu-clk subdriver. Signed-off-by: Marek Szyprowski Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3fbfd9ed82b7..3bd2d84b2a17 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -721,7 +721,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = { DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), - DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3), + DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),