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Tue, 3 Oct 2017 10:00:31 +0000 (GMT) X-AuditID: cbfec7ef-f79ee6d000003120-4b-59d35fbf7ffa Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 30.64.20118.FBF53D95; Tue, 3 Oct 2017 11:00:31 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OX8005VZRSOD560@eusync2.samsung.com>; Tue, 03 Oct 2017 11:00:31 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 6/9] clk: samsung: Rework clkdev alias handling in Exynos5440 driver Date: Tue, 03 Oct 2017 12:00:13 +0200 Message-id: <20171003100016.32029-7-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171003100016.32029-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMIsWRmVeSWpSXmKPExsWy7djP87r74y9HGsyfoWKxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3eLwm3ZWB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4/+acywFH/gqmn88Zm9gvMzTxcjBISFgIvH0nE0XIyeQKSZx4d56ti5GLg4hgWWM Ep+mTWKGcD4zSly428wCUWUisX9nAytc1czdU1kgnAYmiabjp1lBqtgEDCW63naxgdgiAg4S nz+9ZgQpYhZ4yihx4tBzJpCEsECYxL+Z38FsFgFVicZrDWANvAK2Eh8nXmKHWCcv8X7BfUYQ m1PATmLxx+VgqyUEGtkkevc/ZoZ4wkVizntTiHphiVfHt0D1ykhcntwNdXY/o0RTqzaEPYNR 4txbXgjbWuLw8YtgRzML8ElM2jYdaiSvREebEESJh8SPW1+hxjhK/Nz/mwni4YmMEqd3tbJO YJRewMiwilEktbQ4Nz212FCvODG3uDQvXS85P3cTIzAqT/87/n4H49PmkEOMAhyMSjy8Ozwu RQqxJpYVV+YeYpTgYFYS4Z3mdTlSiDclsbIqtSg/vqg0J7X4EKM0B4uSOK9tVFukkEB6Yklq dmpqQWoRTJaJg1OqgbF2t6aXbczMffx7DO62KV3sYTwqHdEgmHB/n/b070tfpi7a8qrGOe7Y up5gkwSz5zObt36u8/9xLE8tdNsTPXnr3aZvk87F/3x1TjyQZ6ox1xtPuYjK3qNLvXy3XDll IJLgdLE6ytgpa6ZJ0ZSTq0ovKPU1fluwTF9+hdD8T+b7/NrfmW1gaFdiKc5INNRiLipOBADC wpJKxgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupiluLIzCtJLcpLzFFi42I5/e/4Fd398ZcjDVqOM1lsnLGe1eL6l+es FufPb2C3+Nhzj9Vixvl9TBZrj9xltzj8pp3Vgd1j06pONo++LasYPT5vkgtgjuKySUnNySxL LdK3S+DK+L/mHEvBB76K5h+P2RsYL/N0MXJySAiYSOzf2cAKYYtJXLi3nq2LkYtDSGAJo8T6 9bNZIJwmJok7jctZQKrYBAwlut52sYHYIgIOEp8/vWYEKWIWeMoocfztVLAiYYEwibO3fjKB 2CwCqhKN1xrAGngFbCU+TrzEDrFOXuL9gvuMIDangJ3E4o/Lwc4QAqppnL+KeQIj7wJGhlWM IqmlxbnpucVGesWJucWleel6yfm5mxiBIbTt2M8tOxi73gUfYhTgYFTi4d3hcSlSiDWxrLgy 9xCjBAezkgjvNK/LkUK8KYmVValF+fFFpTmpxYcYpTlYlMR5e/esjhQSSE8sSc1OTS1ILYLJ MnFwSjUwZpzjzdFRndVbGbfNQvrwoZ+yiz44b5V+lnSm+24U4/2YpDdXDKZ3/I4VuZwYs03v 2OObst2ciypqLS/x+bmk3g/ZFv5GvGEevy3zDjefhaeqfl6cWnls1u9zdznXW2nlyj2M5l54 +bt5xY9D21Nm/Aw4b+SYEBbi/qw81y46+d2jVQZlJtLuSizFGYmGWsxFxYkA39wPfx0CAAA= X-CMS-MailID: 20171003100031eucas1p145edaae6b857c194139d594ebdc9447e X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20171003100031eucas1p145edaae6b857c194139d594ebdc9447e X-RootMTR: 20171003100031eucas1p145edaae6b857c194139d594ebdc9447e References: <20171003100016.32029-1-m.szyprowski@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos5440 still uses old, non-dt CPUfreq driver, which requires clkdev aliases to get access to proper clocks. Create those aliases using samsung_clk_register_alias() function instead of using *_A clock macros, which will be removed soon. Signed-off-by: Marek Szyprowski Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5440.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index a80f3ef20801..b08bd54c5e76 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __ /* mux clocks */ static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = { MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), - MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, - CPU_CLK_STATUS, 0, 1, "armclk"), + MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1), }; /* divider clocks */ @@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = { PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL), }; +/* + * Clock aliases for legacy clkdev look-up. + */ +static const struct samsung_clock_alias exynos5440_aliases[] __initconst = { + ALIAS(CLK_ARM_CLK, NULL, "armclk"), +}; + /* register exynos5440 clocks */ static void __init exynos5440_clk_init(struct device_node *np) { @@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np) ARRAY_SIZE(exynos5440_div_clks)); samsung_clk_register_gate(ctx, exynos5440_gate_clks, ARRAY_SIZE(exynos5440_gate_clks)); + samsung_clk_register_alias(ctx, exynos5440_aliases, + ARRAY_SIZE(exynos5440_aliases)); samsung_clk_of_add_provider(np, ctx);