Message ID | 20171005023314.21663-1-megous@megous.com (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
On Thu, Oct 05, 2017 at 02:33:14AM +0000, megous@megous.com wrote: > From: Ondrej Jirman <megous@megous.com> > > Datasheet specified that parent MUX settings are at bits [10:8], > but current implementation specifies incorrect offset at [10:12]. > Fix this. > > Signed-off-by: Ondrej Jirman <megous@megous.com> Applied, thanks! Maxime
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index b0fbdaea76de..d7938ab57429 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -534,7 +534,7 @@ static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, csi_mclk_table, 0x134, 0, 5, /* M */ - 10, 3, /* mux */ + 8, 3, /* mux */ BIT(15), /* gate */ 0);