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Wed, 11 Oct 2017 09:25:21 +0000 (GMT) X-AuditID: cbfec7f1-f793a6d00000326b-1b-59dde38142be Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id EB.3B.18832.183EDD95; Wed, 11 Oct 2017 10:25:21 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OXN00BGOJI4PG80@eusync4.samsung.com>; Wed, 11 Oct 2017 10:25:21 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , devicetree@vger.kernel.org Subject: [PATCH v3 2/5] clk: samsung: Add dt bindings for Exynos4412 ISP clock controller Date: Wed, 11 Oct 2017 11:25:12 +0200 Message-id: <20171011092515.1698-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171011092515.1698-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsWy7djP87qNj+9GGvyYrmWxccZ6VovrX56z Wsw/co7VYtL9CSwW589vYLf42HOP1WLG+X1MFmuP3GW3OPymndWB02PTqk42j74tqxg9Pm+S C2CO4rJJSc3JLEst0rdL4Mp4dOM8e8FXuYqXMy8xNjDek+xi5OSQEDCRmDV/EzuELSZx4d56 ti5GLg4hgaWMEkde9TJBOJ8ZJe6u3sUI07H8aysjRGIZo8TbxivMEE4Dk8SrX0eZQKrYBAwl ut52sYHYIgIOEp8/vQbrYBZYxCTR/GkiK0hCWCBa4vesc8wgNouAqsS2U+1gK3gFbCTWtb6F Wicv8X7BfTCbU8BW4tWLNrADJQQmsEk8n3yfCaLIRWLZmg2sELawxKvjW6A+kpHo7DgIVdPP KNHUqg1hz2CUOPeWF8K2ljh8/CJYL7MAn8SkbdOBDuIAivNKdLQJQZR4SJydu4EZwnaU6Hq/ AWy8kMAERokLt60nMEovYGRYxSiSWlqcm55abKRXnJhbXJqXrpecn7uJERirp/8d/7iD8f0J q0OMAhyMSjy8AtfvRAqxJpYVV+YeYpTgYFYS4T13426kEG9KYmVValF+fFFpTmrxIUZpDhYl cV7bqLZIIYH0xJLU7NTUgtQimCwTB6dUA+Mso7I93HMvd98wDZxRucSG8/GfTXleZ2b4+92x X6G7UkKrfMJKBztxE/1CK4mzSx6sFvOYsOBT+ZbmA3NdbZqmevtrf3h2LXnWXbUTR+5vtMmM uZ3ttkf11z7+JxIzOH59PXT0WUnQuV1n1H97d35k0pMK0Fohck+o8mDytQ9zTG8Zdm2U5elX YinOSDTUYi4qTgQAaKcddtECAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprMLMWRmVeSWpSXmKPExsVy+t/xa7qNj+9GGsz4yWuxccZ6VovrX56z Wsw/co7VYtL9CSwW589vYLf42HOP1WLG+X1MFmuP3GW3OPymndWB02PTqk42j74tqxg9Pm+S C2CO4rJJSc3JLEst0rdL4Mp4dOM8e8FXuYqXMy8xNjDek+xi5OSQEDCRWP61lRHCFpO4cG89 G4gtJLCEUeLhRIMuRi4gu4lJYuWfDcwgCTYBQ4mut11gRSICDhKfP71mBCliFljGJPH4yjYW kISwQLTE3AlrwKayCKhKbDvVDmbzCthIrGt9C7VNXuL9gvtgNqeArcSrF21Qm20knm/bxjaB kXcBI8MqRpHU0uLc9NxiQ73ixNzi0rx0veT83E2MwKDaduzn5h2MlzYGH2IU4GBU4uEVuH4n Uog1say4MvcQowQHs5II77kbdyOFeFMSK6tSi/Lji0pzUosPMUpzsCiJ8/buWR0pJJCeWJKa nZpakFoEk2Xi4JRqYOw7pBBckdXTyCWgtaNN8+tzWdMtEgVLeyZF6l9eNiHPaJHUk+KGX8sV lRedt/+1O6Zm382P+yfs8HX+OHvn7BvpDkGHD95SW7ls6VE2/hibHTeCeyX9HnW32NRNSOB4 z3Te+DefZd//fTwbzy3jnpnA+0RUPbtiwtXNb2S0dI5OnqTLtceBi0+JpTgj0VCLuag4EQD4 EKB4JgIAAA== X-CMS-MailID: 20171011092521eucas1p12fa702013b7bdbb4f9250e9da3fda8a1 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20171011092521eucas1p12fa702013b7bdbb4f9250e9da3fda8a1 X-RootMTR: 20171011092521eucas1p12fa702013b7bdbb4f9250e9da3fda8a1 References: <20171011092515.1698-1-m.szyprowski@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Because those registers are also located in a different memory region than the main clock controller, support for them can be provided by a separate clock controller. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/clock/exynos4-clock.txt | 43 ++++++++++++++++++++++ include/dt-bindings/clock/exynos4.h | 35 ++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19ed3b2..bc61c952cb0b 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -41,3 +41,46 @@ Example 2: UART controller node that consumes the clock generated by the clock clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; + +Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP) +subsystem. Registers for those clocks are located in the ISP power domain. +Because those registers are also located in a different memory region than +the main clock controller, a separate clock controller has to be defined for +handling them. + +Required Properties: + +- compatible: should be "samsung,exynos4412-isp-clock". + +- reg: physical base address of the ISP clock controller and length of memory + mapped region. + +- #clock-cells: should be 1. + +- clocks: list of the clock controller input clock identifiers, + from common clock bindings, should point to CLK_ACLK200 and + CLK_ACLK400_MCUISP clocks from the main clock controller. + +- clock-names: list of the clock controller input clock names, + as described in clock-bindings.txt, should be "aclk200" and + "aclk400_mcuisp". + +- power-domains: a phandle to ISP power domain node as described by + generic PM domain bindings. + +Example 3: The clock controllers bindings for Exynos4412 SoCs. + + clock: clock-controller@10030000 { + compatible = "samsung,exynos4412-clock"; + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index c40111f36d5e..e9f9d400c322 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -272,4 +272,39 @@ /* must be greater than maximal clock id */ #define CLK_NR_CLKS 461 +/* Exynos4x12 ISP clocks */ +#define CLK_ISP_FIMC_ISP 1 +#define CLK_ISP_FIMC_DRC 2 +#define CLK_ISP_FIMC_FD 3 +#define CLK_ISP_FIMC_LITE0 4 +#define CLK_ISP_FIMC_LITE1 5 +#define CLK_ISP_MCUISP 6 +#define CLK_ISP_GICISP 7 +#define CLK_ISP_SMMU_ISP 8 +#define CLK_ISP_SMMU_DRC 9 +#define CLK_ISP_SMMU_FD 10 +#define CLK_ISP_SMMU_LITE0 11 +#define CLK_ISP_SMMU_LITE1 12 +#define CLK_ISP_PPMUISPMX 13 +#define CLK_ISP_PPMUISPX 14 +#define CLK_ISP_MCUCTL_ISP 15 +#define CLK_ISP_MPWM_ISP 16 +#define CLK_ISP_I2C0_ISP 17 +#define CLK_ISP_I2C1_ISP 18 +#define CLK_ISP_MTCADC_ISP 19 +#define CLK_ISP_PWM_ISP 20 +#define CLK_ISP_WDT_ISP 21 +#define CLK_ISP_UART_ISP 22 +#define CLK_ISP_ASYNCAXIM 23 +#define CLK_ISP_SMMU_ISPCX 24 +#define CLK_ISP_SPI0_ISP 25 +#define CLK_ISP_SPI1_ISP 26 + +#define CLK_ISP_DIV_ISP0 27 +#define CLK_ISP_DIV_ISP1 28 +#define CLK_ISP_DIV_MCUISP0 29 +#define CLK_ISP_DIV_MCUISP1 30 + +#define CLK_NR_ISP_CLKS 31 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */