From patchwork Mon Dec 11 06:48:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 10104315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C8E3E60235 for ; Mon, 11 Dec 2017 06:50:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A733A292FD for ; Mon, 11 Dec 2017 06:50:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A5BD229365; Mon, 11 Dec 2017 06:50:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A391294B8 for ; Mon, 11 Dec 2017 06:50:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752617AbdLKGuW (ORCPT ); Mon, 11 Dec 2017 01:50:22 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:6425 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752512AbdLKGuT (ORCPT ); Mon, 11 Dec 2017 01:50:19 -0500 Received: from localhost.localdomain (10.18.20.164) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Mon, 11 Dec 2017 14:49:40 +0800 From: Yixun Lan To: Neil Armstrong , Jerome Brunet , Kevin Hilman CC: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Carlo Caione , Yixun Lan , Qiufang Dai , Jian Hu , , , , , Subject: [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81 Date: Mon, 11 Dec 2017 14:48:53 +0800 Message-ID: <20171211064853.32111-7-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171211064853.32111-1-yixun.lan@amlogic.com> References: <20171211064853.32111-1-yixun.lan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.20.164] Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Switch the uart_ao pclk to CLK81 since the clock driver is ready. Also move the clock info to the board.dts instead in the soc.dtsi. Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 70eca1f8736a..718bbebff107 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -19,4 +19,6 @@ &uart_AO { status = "okay"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 6fe5ee0c144e..f5b496bfd4de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-axg"; @@ -200,8 +201,6 @@ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; interrupts = ; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; @@ -209,8 +208,6 @@ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x4000 0x0 0x18>; interrupts = ; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; };