| Message ID | 20171211141348.22048-7-yixun.lan@amlogic.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Mon, 2017-12-11 at 22:13 +0800, Yixun Lan wrote: > Switch the uart_ao pclk to CLK81 since the clock driver is ready. > Also move the clock info to the board.dts instead in the soc.dtsi. Same comment as for ethmac, is it really wise ? Isn't the clock setup the same for the axg family ? > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 12/15/17 00:47, Jerome Brunet wrote: > On Mon, 2017-12-11 at 22:13 +0800, Yixun Lan wrote: >> Switch the uart_ao pclk to CLK81 since the clock driver is ready. >> Also move the clock info to the board.dts instead in the soc.dtsi. > > Same comment as for ethmac, is it really wise ? > Isn't the clock setup the same for the axg family ? > HI Jerome: yes, should be same for AXG family HI Kevin: could you take the patch [5/6]? then I just need to resend for this one Yixun -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Yixun Lan <yixun.lan@amlogic.com> writes: > On 12/15/17 00:47, Jerome Brunet wrote: >> On Mon, 2017-12-11 at 22:13 +0800, Yixun Lan wrote: >>> Switch the uart_ao pclk to CLK81 since the clock driver is ready. >>> Also move the clock info to the board.dts instead in the soc.dtsi. >> >> Same comment as for ethmac, is it really wise ? >> Isn't the clock setup the same for the axg family ? >> > HI Jerome: > yes, should be same for AXG family > > > HI Kevin: > could you take the patch [5/6]? then I just need to resend for this one Yes, I've applied PATCH 5/6. Kevin -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 70eca1f8736a..718bbebff107 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -19,4 +19,6 @@ &uart_AO { status = "okay"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 6fe5ee0c144e..f5b496bfd4de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/axg-clkc.h> / { compatible = "amlogic,meson-axg"; @@ -200,8 +201,6 @@ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; @@ -209,8 +208,6 @@ compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x4000 0x0 0x18>; interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; };
Switch the uart_ao pclk to CLK81 since the clock driver is ready. Also move the clock info to the board.dts instead in the soc.dtsi. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +---- 2 files changed, 3 insertions(+), 4 deletions(-)