| Message ID | 20180323143816.200573-8-yixun.lan@amlogic.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Fri, 2018-03-23 at 22:38 +0800, Yixun Lan wrote: > The ao_clk81 in AO domain have two clock source, > one from a 32K alt crystal we name it as ao_alt_clk, > another is the clk81 signal from EE domain. > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > index b3d394f5d95a..48584d5a329b 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi > @@ -109,6 +109,13 @@ > #clock-cells = <0>; > }; > > + ao_alt_xtal: ao_alt_xtal-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32000000>; > + clock-output-names = "ao_alt_xtal"; > + #clock-cells = <0>; > + }; In DT, we seem to be using 'ao' and 'AO' to designate the Always On domain. Maybe we should be try be consistent about this. Anyway, this patch looks good but does not need to be part of the clkc_ao series, it could go in independently. Acked-by: Jerome Brunet <jbrunet@baylibre.com> > + > soc { > compatible = "simple-bus"; > #address-cells = <2>; -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index b3d394f5d95a..48584d5a329b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -109,6 +109,13 @@ #clock-cells = <0>; }; + ao_alt_xtal: ao_alt_xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <32000000>; + clock-output-names = "ao_alt_xtal"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;
The ao_clk81 in AO domain have two clock source, one from a 32K alt crystal we name it as ao_alt_clk, another is the clk81 signal from EE domain. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)