From patchwork Wed Apr 18 12:49:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 10348097 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 896BB6053F for ; Wed, 18 Apr 2018 12:49:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 77A8620163 for ; Wed, 18 Apr 2018 12:49:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6A04D28554; Wed, 18 Apr 2018 12:49:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D2CF20163 for ; Wed, 18 Apr 2018 12:49:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753872AbeDRMtS (ORCPT ); Wed, 18 Apr 2018 08:49:18 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:36494 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753815AbeDRMtR (ORCPT ); Wed, 18 Apr 2018 08:49:17 -0400 Received: from trochilidae.toradex.int (unknown [IPv6:2001:1620:c6e:10::3]) by mail.kmu-office.ch (Postfix) with ESMTPSA id 045AF5C0B22; Wed, 18 Apr 2018 14:49:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1524055756; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:content-type:content-transfer-encoding: in-reply-to:references; bh=OfPIMYE3KFxKQkfuuspZAKH2Zsncts/W2cn9+VxyZC8=; b=rL9Zbi2oS+7Yg0xzCSz65BP1hBdNjeEd45ZxTCYhPCKm2QsWaQtT8uLESPSO5huQFM7IKD Ovu70kTuWkNq39xYI2oTjwrf0h7SM/FvMNFuMk1CsiHjz+6+EsJh4FCn17Jt42UJIrc6nu 1Zxs8lusug0Kn5mmOHnsjfpTapcBX6Q= From: Stefan Agner To: shawnguo@kernel.org, kernel@pengutronix.de Cc: fabio.estevam@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Stefan Agner Subject: [PATCH] clk: imx6ull: use OSC clock during AXI rate change Date: Wed, 18 Apr 2018 14:49:08 +0200 Message-Id: <20180418124908.3079-1-stefan@agner.ch> X-Mailer: git-send-email 2.17.0 X-Spamd-Result: default: False [-2.10 / 15.00]; RCVD_TLS_ALL(0.00)[]; ASN(0.00)[asn:13030, ipnet:2001:1620::/32, country:CH]; RCVD_COUNT_ZERO(0.00)[0]; FROM_HAS_DN(0.00)[]; MID_CONTAINS_FROM(1.00)[]; TO_DN_SOME(0.00)[]; MIME_GOOD(-0.10)[text/plain]; FROM_EQ_ENVFROM(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; BAYES_HAM(-3.00)[100.00%]; ARC_NA(0.00)[]; DKIM_SIGNED(0.00)[]; RCPT_COUNT_SEVEN(0.00)[9] Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On i.MX6 ULL using PLL3 seems to cause a freeze when setting the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux"), probably because the clock is now forced to be on. Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux") Signed-off-by: Stefan Agner --- This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also: https://patchwork.kernel.org/patch/10295927/ drivers/clk/imx/clk-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 114ecbb94ec5..12320118f8de 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000); /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */ - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]); clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]); clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]); clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);