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Thu, 6 Sep 2018 16:02:46 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges3new.samsung.com (EUCPMTA) with SMTP id 1B.C1.04806.6AF419B5; Thu, 6 Sep 2018 17:02:46 +0100 (BST) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180906160245eucas1p2800b51c95c9433501b06d92ca0f1aa94~R2wXJ2auX0478104781eucas1p2g; Thu, 6 Sep 2018 16:02:45 +0000 (GMT) X-AuditID: cbfec7f5-367ff700000012c6-0b-5b914fa6b10a Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id C0.6D.04128.5AF419B5; Thu, 6 Sep 2018 17:02:45 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PEN0037W5WGAX30@eusync1.samsung.com>; Thu, 06 Sep 2018 17:02:45 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v2 2/2] clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs Date: Thu, 06 Sep 2018 18:02:36 +0200 Message-id: <20180906160236.4326-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20180906160236.4326-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRmVeSWpSXmKPExsWy7djP87rL/CdGGzz7KWCxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3aL96UtmB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr48T5S+wFB6Qrns9aztrA+Easi5GTQ0LARKL9xi/GLkYuDiGBFYwSk3/cZIdwPjNK zLp9nAWm6suzuUwQiWWMEu/2b2OGcBqYJG41tzGBVLEJGEp0ve1iA7FFBBwkPn96DTaXWeAx o8TWk1+ZQRLCAgkSc/e1gjWwCKhK9Lw7zg5i8wrYSOw/9g9qnbzE6g0HwOo5BWwlbu97xQIy SELgK6vEu+N7mSCKXCR+XXkNZQtLvDq+hR3ClpG4PLkbqqGZUaJ9xix2CKcH6Iw5O9ggqqwl Dh+/yApiMwvwSUzaNh1oHQdQnFeio00IosRDYu/pV2wQf05glNh5eA/zBEbJBYwMqxjFU0uL c9NTi43zUsv1ihNzi0vz0vWS83M3MQJj7vS/4193MO77k3SIUYCDUYmH94HRxGgh1sSy4src Q4wSHMxKIrzu1ROihXhTEiurUovy44tKc1KLDzFKc7AoifPyaaVFCwmkJ5akZqemFqQWwWSZ ODilGhjb7cp1NocnyJnlvfn84ujiv4/mS0rwKcT82T7lmaCyoXlG7ZxwXc7X81WmWZ6ranfu v8N65Gftr93Z50o7dJqeRqzW2toUs47H46LK+gXlInfdxH3yjRW+/vWYFLMu0aI3YB/7wwUh sZ+Pvf303qe8ve6xVd9p50MXl0+VPd6WeX4Fs19P40QlluKMREMt5qLiRAAZdoYktQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLJMWRmVeSWpSXmKPExsVy+t/xy7pL/SdGG3xuN7TYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbtH+9CWzA7vHplWdbB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CVceL8JfaCA9IVz2ctZ21gfCPWxcjJISFgIvHl2VwmEFtIYAmjxLKVJl2MXEB2E5PE y5UrwBJsAoYSXW+72EBsEQEHic+fXjOCFDELPGaUOLd4AytIQlggQWLuvlawBhYBVYmed8fZ QWxeARuJ/cf+sUBsk5dYveEAM4jNKWArcXvfKxaIzTYSF3pPsU5g5FnAyLCKUSS1tDg3PbfY SK84Mbe4NC9dLzk/dxMjMFC2Hfu5ZQdj17vgQ4wCHIxKPLwWphOjhVgTy4orcw8xSnAwK4nw uldPiBbiTUmsrEotyo8vKs1JLT7EKM3BoiTOe96gMkpIID2xJDU7NbUgtQgmy8TBKdXAOP/I /Sq/Fsem+lthjwp38BwsXufeyZA80ZkzZAdb0AMbkXKDt69+2HfEbvrml+bjmH1u3lYBu2CP 24/sIoPPCvLOr6g9nXbw3NHGhEMyG3TeLvJ2F31j1qP94JbLr24j7/T7zkcfqa3aqSKk15zv 9bXZhfeB/rYb9g8dVot5b+e0XVF22KZMiaU4I9FQi7moOBEAfHznXhACAAA= X-CMS-MailID: 20180906160245eucas1p2800b51c95c9433501b06d92ca0f1aa94 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180906160245eucas1p2800b51c95c9433501b06d92ca0f1aa94 References: <20180906160236.4326-1-m.szyprowski@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Before entering system suspend, one has to ensure that some clocks from TOP, CPIF and PERIC CMUs are enabled. This is needed by the firmware to properly perform system suspend operation. Instead of adding more and more clocks with CRITICAL flag, simply enable those clocks directly in respective CMU registers using 'suspend_regs' feature. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5433.c | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 426980514e67..13384f4911c7 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -177,6 +177,15 @@ static const unsigned long top_clk_regs[] __initconst = { ENABLE_CMU_TOP_DIV_STAT, }; +static const struct samsung_clk_reg_dump top_suspend_regs[] = { + /* force all aclk clocks enabled */ + { ENABLE_ACLK_TOP, 0x67ecffed }, + /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ + { ISP_PLL_CON0, 0x85cc0502 }, + /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ + { AUD_PLL_CON0, 0x84830202 }, +}; + /* list of all parent clock list */ PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; @@ -792,6 +801,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_clk_ids = TOP_NR_CLK, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), + .suspend_regs = top_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs), }; static void __init exynos5433_cmu_top_init(struct device_node *np) @@ -822,6 +833,13 @@ static const unsigned long cpif_clk_regs[] __initconst = { ENABLE_SCLK_CPIF, }; +static const struct samsung_clk_reg_dump cpif_suspend_regs[] = { + /* force all sclk clocks enabled */ + { ENABLE_SCLK_CPIF, 0x3ff }, + /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */ + { MPHY_PLL_CON0, 0x81c70601 }, +}; + /* list of all parent clock list */ PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; @@ -862,6 +880,8 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = { .nr_clk_ids = CPIF_NR_CLK, .clk_regs = cpif_clk_regs, .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), + .suspend_regs = cpif_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs), }; static void __init exynos5433_cmu_cpif_init(struct device_node *np) @@ -1547,6 +1567,13 @@ static const unsigned long peric_clk_regs[] __initconst = { ENABLE_IP_PERIC2, }; +static const struct samsung_clk_reg_dump peric_suspend_regs[] = { + /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */ + { ENABLE_PCLK_PERIC0, 0xe00ff000 }, + /* sclk: uart2-0 */ + { ENABLE_SCLK_PERIC, 0x7 }, +}; + static const struct samsung_div_clock peric_div_clks[] __initconst = { /* DIV_PERIC */ DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), @@ -1705,6 +1732,8 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { .nr_clk_ids = PERIC_NR_CLK, .clk_regs = peric_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), + .suspend_regs = peric_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs), }; static void __init exynos5433_cmu_peric_init(struct device_node *np)