From patchwork Sun Oct 7 09:38:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 10629469 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEC23933 for ; Sun, 7 Oct 2018 09:40:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A21C729190 for ; Sun, 7 Oct 2018 09:40:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95809291AF; Sun, 7 Oct 2018 09:40:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2013029190 for ; Sun, 7 Oct 2018 09:40:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728554AbeJGQrB (ORCPT ); Sun, 7 Oct 2018 12:47:01 -0400 Received: from mailoutvs7.siol.net ([185.57.226.198]:40121 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728533AbeJGQrA (ORCPT ); Sun, 7 Oct 2018 12:47:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 725CD52048D; Sun, 7 Oct 2018 11:40:15 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta10.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta10.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id HaVr_KbXsn5D; Sun, 7 Oct 2018 11:40:15 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id EE874520456; Sun, 7 Oct 2018 11:40:14 +0200 (CEST) Received: from localhost.localdomain (cpe1-8-82.cable.triera.net [213.161.8.82]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 8C7C352048D; Sun, 7 Oct 2018 11:40:12 +0200 (CEST) From: Jernej Skrabec To: maxime.ripard@bootlin.com, wens@csie.org Cc: robh+dt@kernel.org, sboyd@kernel.org, airlied@linux.ie, architt@codeaurora.org, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com Subject: [PATCH v2 23/29] drm/sun4i: Add support for H6 HDMI PHY Date: Sun, 7 Oct 2018 11:38:59 +0200 Message-Id: <20181007093905.11253-24-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181007093905.11253-1-jernej.skrabec@siol.net> References: <20181007093905.11253-1-jernej.skrabec@siol.net> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP H6 has Synopsys DWC HDMI 2.0 TX PHY. There is no freely available documentation for it, only code found in BSP kernel. However, judging by the code, PHY is very similar to older Synopsys HDMI PHY described in i.MX6 documentation. Most registers seem to be the same. According to i.MX6 documentation, mpll settings are based on pixel clock and are not specific to each SoC. Because of that, mpll table in this commit is based on that documentation and not on BSP code. Other PHY settings were derived from BSP PHY driver code. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 137 +++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 635825b55648..66ea3a902e36 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -14,6 +14,122 @@ */ #define I2C_ADDR 0x69 +static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = { + { + 30666000, { + { 0x00b3, 0x0000 }, + { 0x2153, 0x0000 }, + { 0x40f3, 0x0000 }, + }, + }, { + 36800000, { + { 0x00b3, 0x0000 }, + { 0x2153, 0x0000 }, + { 0x40a2, 0x0001 }, + }, + }, { + 46000000, { + { 0x00b3, 0x0000 }, + { 0x2142, 0x0001 }, + { 0x40a2, 0x0001 }, + }, + }, { + 61333000, { + { 0x0072, 0x0001 }, + { 0x2142, 0x0001 }, + { 0x40a2, 0x0001 }, + }, + }, { + 73600000, { + { 0x0072, 0x0001 }, + { 0x2142, 0x0001 }, + { 0x4061, 0x0002 }, + }, + }, { + 92000000, { + { 0x0072, 0x0001 }, + { 0x2145, 0x0002 }, + { 0x4061, 0x0002 }, + }, + }, { + 122666000, { + { 0x0051, 0x0002 }, + { 0x2145, 0x0002 }, + { 0x4061, 0x0002 }, + }, + }, { + 147200000, { + { 0x0051, 0x0002 }, + { 0x2145, 0x0002 }, + { 0x4064, 0x0003 }, + }, + }, { + 184000000, { + { 0x0051, 0x0002 }, + { 0x214c, 0x0003 }, + { 0x4064, 0x0003 }, + }, + }, { + 226666000, { + { 0x0040, 0x0003 }, + { 0x214c, 0x0003 }, + { 0x4064, 0x0003 }, + }, + }, { + 272000000, { + { 0x0040, 0x0003 }, + { 0x214c, 0x0003 }, + { 0x5a64, 0x0003 }, + }, + }, { + 340000000, { + { 0x0040, 0x0003 }, + { 0x3b4c, 0x0003 }, + { 0x5a64, 0x0003 }, + }, + }, { + 594000000, { + { 0x1a40, 0x0003 }, + { 0x3b4c, 0x0003 }, + { 0x5a64, 0x0003 }, + }, + }, { + ~0UL, { + { 0x0000, 0x0000 }, + { 0x0000, 0x0000 }, + { 0x0000, 0x0000 }, + }, + } +}; + +static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { 25175000, { 0x0000, 0x0000, 0x0000 }, }, + { 27000000, { 0x0012, 0x0000, 0x0000 }, }, + { 59400000, { 0x0008, 0x0008, 0x0008 }, }, + { 72000000, { 0x0008, 0x0008, 0x001b }, }, + { 74250000, { 0x0013, 0x0013, 0x0013 }, }, + { 90000000, { 0x0008, 0x001a, 0x001b }, }, + { 118800000, { 0x001b, 0x001a, 0x001b }, }, + { 144000000, { 0x001b, 0x001a, 0x0034 }, }, + { 180000000, { 0x001b, 0x0033, 0x0034 }, }, + { 216000000, { 0x0036, 0x0033, 0x0034 }, }, + { 237600000, { 0x0036, 0x0033, 0x001b }, }, + { 288000000, { 0x0036, 0x001b, 0x001b }, }, + { 297000000, { 0x0019, 0x001b, 0x0019 }, }, + { 330000000, { 0x0036, 0x001b, 0x001b }, }, + { 594000000, { 0x003f, 0x001b, 0x001b }, }, + { ~0UL, { 0x0000, 0x0000, 0x0000 }, } +}; + +static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = { + /*pixelclk symbol term vlev*/ + { 74250000, 0x8009, 0x0004, 0x0232}, + { 148500000, 0x8029, 0x0004, 0x0273}, + { 594000000, 0x8039, 0x0004, 0x014a}, + { ~0UL, 0x0000, 0x0000, 0x0000} +}; + static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi, struct sun8i_hdmi_phy *phy, unsigned int clk_rate) @@ -290,6 +406,16 @@ static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC); } +static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy) +{ + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, + SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, + SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN); + + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, + 0xffff0000, 0x80c00000); +} + static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy) { sun8i_hdmi_phy_unlock(phy); @@ -446,6 +572,13 @@ static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { .phy_config = &sun8i_hdmi_phy_config_h3, }; +static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = { + .cur_ctr = sun50i_h6_cur_ctr, + .mpll_cfg = sun50i_h6_mpll_cfg, + .phy_cfg = sun50i_h6_phy_config, + .phy_init = &sun50i_hdmi_phy_init_h6, +}; + static const struct of_device_id sun8i_hdmi_phy_of_table[] = { { .compatible = "allwinner,sun8i-a83t-hdmi-phy", @@ -463,6 +596,10 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = { .compatible = "allwinner,sun50i-a64-hdmi-phy", .data = &sun50i_a64_hdmi_phy, }, + { + .compatible = "allwinner,sun50i-h6-hdmi-phy", + .data = &sun50i_h6_hdmi_phy, + }, { /* sentinel */ } };