From patchwork Mon Dec 17 12:36:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 10733343 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C01B6C2 for ; Mon, 17 Dec 2018 12:38:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1B7229DA6 for ; Mon, 17 Dec 2018 12:38:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E603729DB2; Mon, 17 Dec 2018 12:38:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 913D729DA6 for ; Mon, 17 Dec 2018 12:38:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732949AbeLQMhs (ORCPT ); Mon, 17 Dec 2018 07:37:48 -0500 Received: from gloria.sntech.de ([185.11.138.130]:57702 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727303AbeLQMhU (ORCPT ); Mon, 17 Dec 2018 07:37:20 -0500 Received: from wf0848.dip.tu-dresden.de ([141.76.183.80] helo=phil.dip.tu-dresden.de) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1gYs8t-0003o4-8O; Mon, 17 Dec 2018 13:37:03 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org, hjc@rock-chips.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, robh+dt@kernel.org, mark.rutland@arm.com, architt@codeaurora.org, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, linux-clk@vger.kernel.org, Heiko Stuebner Subject: [PATCH 07/15] drm/rockchip: dw-mipi-dsi: add support for rk3368-variant Date: Mon, 17 Dec 2018 13:36:42 +0100 Message-Id: <20181217123650.6773-8-heiko@sntech.de> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181217123650.6773-1-heiko@sntech.de> References: <20181217123650.6773-1-heiko@sntech.de> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the compatible and grf values and allow the driver to also not select a specific crtc input on systems with only one vop. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- .../display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 25 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 6bb59ab39f2f..869fbc256d51 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -5,6 +5,7 @@ Required properties: - #address-cells: Should be <1>. - #size-cells: Should be <0>. - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi". + "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi". "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi". - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 7ee359bcee62..041647bfce71 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -142,6 +142,11 @@ #define RK3288_DSI0_LCDC_SEL BIT(6) #define RK3288_DSI1_LCDC_SEL BIT(9) +#define RK3368_GRF_SOC_CON7 0x41c +#define RK3368_DSI_TURNDISABLE BIT(5) +#define RK3368_DSI_FORCERXMODE BIT(6) +#define RK3368_DSI_FORCETXSTOPMODE (0xf << 7) + #define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_DSI0_LCDC_SEL BIT(0) #define RK3399_DSI1_LCDC_SEL BIT(4) @@ -192,7 +197,7 @@ enum { struct rockchip_dw_dsi_chip_data { u32 reg; - u32 lcdsel_grf_reg; + int lcdsel_grf_reg; u32 lcdsel_big; u32 lcdsel_lit; @@ -566,7 +571,7 @@ static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi, int mux) { - if (dsi->cdata->lcdsel_grf_reg) + if (dsi->cdata->lcdsel_grf_reg >= 0) regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); @@ -1008,6 +1013,19 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = { + { + .reg = 0xff960000, + .lcdsel_grf_reg = -1, + .lanecfg1_grf_reg = RK3368_GRF_SOC_CON7, + .lanecfg1 = HIWORD_UPDATE(0, RK3368_DSI_TURNDISABLE | + RK3368_DSI_FORCERXMODE | + RK3368_DSI_FORCETXSTOPMODE), + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { .reg = 0xff960000, @@ -1058,6 +1076,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3288-mipi-dsi", .data = &rk3288_chip_data, + }, { + .compatible = "rockchip,rk3368-mipi-dsi", + .data = &rk3368_chip_data, }, { .compatible = "rockchip,rk3399-mipi-dsi", .data = &rk3399_chip_data,