| Message ID | 20190125234509.26419-8-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | QCS404 PCIe PHY and controller | expand |
Quoting Bjorn Andersson (2019-01-25 15:45:09) > @@ -771,6 +788,56 @@ > status = "disabled"; > }; > }; > + > + pcie: pci@10000000 { > + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; > + reg = <0x10000000 0xf1d Nitpick: Can you format these like <0x10000000 0xf1d>, <0x10000f20 0xa8>, etc? > + 0x10000f20 0xa8 > + 0x07780000 0x2000 > + 0x10001000 0x2000>; > + reg-names = "dbi", "elbi", "parf", "config"; > + device_type = "pci"; > + linux,pci-domain = <0>; > + bus-range = <0x00 0xff>; > + num-lanes = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */ Same for this one? It's nice to know what the size of the cells are. > + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ > +
On 25-01-19, 15:45, Bjorn Andersson wrote: > The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to > the platform dtsi and enable them for the EVB with the perst gpio > and analog supplies defined. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++ > arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++ > 2 files changed, 92 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi > index 50b3589c7f15..579ddaf4f5fa 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi > @@ -21,6 +21,22 @@ > }; > }; > > +&pcie { > + status = "ok"; > + > + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&perst_state>; > +}; > + > +&pcie_phy { > + status = "ok"; > + > + vdda-vp-supply = <&vreg_l3_1p05>; > + vdda-vph-supply = <&vreg_l5_1p8>; > +}; I would prefer the patches be split to qcs404 adding PCIe nodes and then add the board node for EVB... > + > &remoteproc_adsp { > status = "ok"; > }; > @@ -137,6 +153,15 @@ > }; > > &tlmm { > + perst_state: perst { > + pins = "gpio43"; > + function = "gpio"; > + > + drive-strength = <2>; > + bias-disable; > + output-low; > + }; > + > sdc1_on: sdc1-on { > clk { > pins = "sdc1_clk"; > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index 76699435c8bd..7b219865ba7e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -3,6 +3,7 @@ > > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,gcc-qcs404.h> > +#include <dt-bindings/gpio/gpio.h> > > / { > interrupt-parent = <&intc>; > @@ -377,6 +378,7 @@ > compatible = "qcom,gcc-qcs404"; > reg = <0x01800000 0x80000>; > #clock-cells = <1>; > + #reset-cells = <1>; > > assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; > assigned-clock-rates = <19200000>; > @@ -405,6 +407,21 @@ > #interrupt-cells = <4>; > }; > > + pcie_phy: phy@7786000 { > + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; > + reg = <0x07786000 0xb8>; > + > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; > + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, > + <&gcc GCC_PCIE_0_PIPE_ARES>; > + reset-names = "phy", "pipe"; > + > + clock-output-names = "pcie_0_pipe_clk"; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > sdcc1: sdcc@7804000 { > compatible = "qcom,sdhci-msm-v5"; > reg = <0x07804000 0x1000>, <0x7805000 0x1000>; > @@ -771,6 +788,56 @@ > status = "disabled"; > }; > }; > + > + pcie: pci@10000000 { > + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; > + reg = <0x10000000 0xf1d > + 0x10000f20 0xa8 > + 0x07780000 0x2000 > + 0x10001000 0x2000>; > + reg-names = "dbi", "elbi", "parf", "config"; > + device_type = "pci"; > + linux,pci-domain = <0>; > + bus-range = <0x00 0xff>; > + num-lanes = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */ > + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ > + > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ > + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ > + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; > + clock-names = "iface", "aux", "master_bus", "slave_bus"; > + > + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, > + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, > + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, > + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, > + <&gcc GCC_PCIE_0_BCR>, > + <&gcc GCC_PCIE_0_AHB_ARES>; > + reset-names = "axi_m", > + "axi_s", > + "axi_m_sticky", > + "pipe_sticky", > + "pwr", > + "ahb"; > + > + phys = <&pcie_phy>; > + phy-names = "pciephy"; > + > + status = "disabled"; > + }; > }; > > timer { > -- > 2.18.0
On Fri, Jan 25, 2019 at 03:45:09PM -0800, Bjorn Andersson wrote: > The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to > the platform dtsi and enable them for the EVB with the perst gpio > and analog supplies defined. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++ > arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++ > 2 files changed, 92 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi > index 50b3589c7f15..579ddaf4f5fa 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi > @@ -21,6 +21,22 @@ > }; > }; > > +&pcie { > + status = "ok"; > + > + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&perst_state>; > +}; > + > +&pcie_phy { > + status = "ok"; > + > + vdda-vp-supply = <&vreg_l3_1p05>; > + vdda-vph-supply = <&vreg_l5_1p8>; > +}; > + > &remoteproc_adsp { > status = "ok"; > }; > @@ -137,6 +153,15 @@ > }; > > &tlmm { > + perst_state: perst { > + pins = "gpio43"; > + function = "gpio"; > + > + drive-strength = <2>; > + bias-disable; > + output-low; > + }; > + > sdc1_on: sdc1-on { > clk { > pins = "sdc1_clk"; > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index 76699435c8bd..7b219865ba7e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -3,6 +3,7 @@ > > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,gcc-qcs404.h> > +#include <dt-bindings/gpio/gpio.h> > > / { > interrupt-parent = <&intc>; > @@ -377,6 +378,7 @@ > compatible = "qcom,gcc-qcs404"; > reg = <0x01800000 0x80000>; > #clock-cells = <1>; > + #reset-cells = <1>; > > assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; > assigned-clock-rates = <19200000>; > @@ -405,6 +407,21 @@ > #interrupt-cells = <4>; > }; > > + pcie_phy: phy@7786000 { > + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; > + reg = <0x07786000 0xb8>; > + > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; > + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, > + <&gcc GCC_PCIE_0_PIPE_ARES>; > + reset-names = "phy", "pipe"; > + > + clock-output-names = "pcie_0_pipe_clk"; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > sdcc1: sdcc@7804000 { > compatible = "qcom,sdhci-msm-v5"; > reg = <0x07804000 0x1000>, <0x7805000 0x1000>; > @@ -771,6 +788,56 @@ > status = "disabled"; > }; > }; > + > + pcie: pci@10000000 { > + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; > + reg = <0x10000000 0xf1d > + 0x10000f20 0xa8 > + 0x07780000 0x2000 > + 0x10001000 0x2000>; > + reg-names = "dbi", "elbi", "parf", "config"; > + device_type = "pci"; > + linux,pci-domain = <0>; Since we only have single PCIe controller, I don't think we need to specify a pci-domain. With that: Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> > + bus-range = <0x00 0xff>; > + num-lanes = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */ > + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ > + > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ > + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ > + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; > + clock-names = "iface", "aux", "master_bus", "slave_bus"; > + > + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, > + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, > + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, > + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, > + <&gcc GCC_PCIE_0_BCR>, > + <&gcc GCC_PCIE_0_AHB_ARES>; > + reset-names = "axi_m", > + "axi_s", > + "axi_m_sticky", > + "pipe_sticky", > + "pwr", > + "ahb"; > + > + phys = <&pcie_phy>; > + phy-names = "pciephy"; > + > + status = "disabled"; > + }; > }; > > timer { > -- > 2.18.0 >
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 50b3589c7f15..579ddaf4f5fa 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -21,6 +21,22 @@ }; }; +&pcie { + status = "ok"; + + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&perst_state>; +}; + +&pcie_phy { + status = "ok"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; +}; + &remoteproc_adsp { status = "ok"; }; @@ -137,6 +153,15 @@ }; &tlmm { + perst_state: perst { + pins = "gpio43"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 76699435c8bd..7b219865ba7e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-qcs404.h> +#include <dt-bindings/gpio/gpio.h> / { interrupt-parent = <&intc>; @@ -377,6 +378,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; @@ -405,6 +407,21 @@ #interrupt-cells = <4>; }; + pcie_phy: phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + + status = "disabled"; + }; + sdcc1: sdcc@7804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; @@ -771,6 +788,56 @@ status = "disabled"; }; }; + + pcie: pci@10000000 { + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + reg = <0x10000000 0xf1d + 0x10000f20 0xa8 + 0x07780000 0x2000 + 0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */ + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; }; timer {
The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to the platform dtsi and enable them for the EVB with the perst gpio and analog supplies defined. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++ 2 files changed, 92 insertions(+)