| Message ID | 20190701113606.4130-1-paul@crapouillou.net (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | clk: ingenic/jz4740: Fix "pll half" divider not read/written properly | expand |
Quoting Paul Cercueil (2019-07-01 04:36:06) > The code was setting the bit 21 of the CPCCR register to use a divider > of 2 for the "pll half" clock, and clearing the bit to use a divider > of 1. > > This is the opposite of how this register field works: a cleared bit > means that the /2 divider is used, and a set bit means that the divider > is 1. > > Restore the correct behaviour using the newly introduced .div_table > field. > > Signed-off-by: Paul Cercueil <paul@crapouillou.net> > --- Applied to clk-next. Does this need a fixes tag?
Le mer. 7 août 2019 à 23:33, Stephen Boyd <sboyd@kernel.org> a écrit : > Quoting Paul Cercueil (2019-07-01 04:36:06) >> The code was setting the bit 21 of the CPCCR register to use a >> divider >> of 2 for the "pll half" clock, and clearing the bit to use a divider >> of 1. >> >> This is the opposite of how this register field works: a cleared bit >> means that the /2 divider is used, and a set bit means that the >> divider >> is 1. >> >> Restore the correct behaviour using the newly introduced .div_table >> field. >> >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> >> --- > > Applied to clk-next. Does this need a fixes tag? It depends on commit a9fa2893fcc6 ("clk: ingenic: Add support for divider tables") which was sent without a fixes tag, so it'd be a bit difficult. Probably not worth the trouble. -Paul
Quoting Paul Cercueil (2019-08-07 16:28:10) > > > Le mer. 7 août 2019 à 23:33, Stephen Boyd <sboyd@kernel.org> a écrit > : > > Quoting Paul Cercueil (2019-07-01 04:36:06) > >> The code was setting the bit 21 of the CPCCR register to use a > >> divider > >> of 2 for the "pll half" clock, and clearing the bit to use a divider > >> of 1. > >> > >> This is the opposite of how this register field works: a cleared bit > >> means that the /2 divider is used, and a set bit means that the > >> divider > >> is 1. > >> > >> Restore the correct behaviour using the newly introduced .div_table > >> field. > >> > >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> > >> --- > > > > Applied to clk-next. Does this need a fixes tag? > > It depends on commit a9fa2893fcc6 ("clk: ingenic: Add support for > divider tables") which was sent without a fixes tag, so it'd be > a bit difficult. Probably not worth the trouble. > Does it need to go in as a fix for this -rc series then? Or is it not causing issues for you so it's ok to wait until next merge window?
Le jeu. 8 août 2019 à 6:08, Stephen Boyd <sboyd@kernel.org> a écrit : > Quoting Paul Cercueil (2019-08-07 16:28:10) >> >> >> Le mer. 7 août 2019 à 23:33, Stephen Boyd <sboyd@kernel.org> a >> écrit >> : >> > Quoting Paul Cercueil (2019-07-01 04:36:06) >> >> The code was setting the bit 21 of the CPCCR register to use a >> >> divider >> >> of 2 for the "pll half" clock, and clearing the bit to use a >> divider >> >> of 1. >> >> >> >> This is the opposite of how this register field works: a >> cleared bit >> >> means that the /2 divider is used, and a set bit means that the >> >> divider >> >> is 1. >> >> >> >> Restore the correct behaviour using the newly introduced >> .div_table >> >> field. >> >> >> >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> >> >> --- >> > >> > Applied to clk-next. Does this need a fixes tag? >> >> It depends on commit a9fa2893fcc6 ("clk: ingenic: Add support for >> divider tables") which was sent without a fixes tag, so it'd be >> a bit difficult. Probably not worth the trouble. >> > > Does it need to go in as a fix for this -rc series then? Or is it not > causing issues for you so it's ok to wait until next merge window? It can wait for the next merge window, yes. -Paul
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index a7f8ce60c957..0957ba4a40a5 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -53,6 +53,10 @@ static const u8 jz4740_cgu_cpccr_div_table[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, }; +static const u8 jz4740_cgu_pll_half_div_table[] = { + 2, 1, +}; + static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { /* External clocks */ @@ -86,7 +90,10 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, + jz4740_cgu_pll_half_div_table, + }, }, [JZ4740_CLK_CCLK] = {
The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> --- drivers/clk/ingenic/jz4740-cgu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)