From patchwork Mon Jul 22 09:54:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 11052067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 15F9F138D for ; Mon, 22 Jul 2019 09:55:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 042B328421 for ; Mon, 22 Jul 2019 09:55:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ECD1F284FC; Mon, 22 Jul 2019 09:55:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 38C2A28481 for ; Mon, 22 Jul 2019 09:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729075AbfGVJyd (ORCPT ); Mon, 22 Jul 2019 05:54:33 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:32885 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728228AbfGVJyb (ORCPT ); Mon, 22 Jul 2019 05:54:31 -0400 Received: by mail-wr1-f66.google.com with SMTP id n9so38791540wru.0 for ; Mon, 22 Jul 2019 02:54:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cIceYeZmXLnDB8KmyjeQxrFIl+tdDqzy/AgzjLz1uyc=; b=09eZ7CUQJWjEDPknM+glm7nGARL3191dfdnzDoDTIcXUf2VN/coQPKSBZPFyz9NNfC GEpjW3GMEewKb1ip9yr6C+f0EGNH+oJMtSnZh4o4fmfolLpJYq0qj5qoRXtmoLrSMamp nUc+JDRBop0pxkonQ1UlKoFZoohi6DPwc8SiO9p5MW2Qs9Fyk68m5bmzKtfpJdJe+5sx E1SspGW/gU3dRoQRjzUmh6F7t40J6L8GQph5JtuYVKFiYXGuDpGmx/sRuMOnRlALG4rS kWCmtJw73zCURV1MhJEG/rSXxW8fgPTIc1eu0Uogi/W6QdiGka/jpW2NiCDfN9FqAR2+ YRUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cIceYeZmXLnDB8KmyjeQxrFIl+tdDqzy/AgzjLz1uyc=; b=Dv5NUHpSwna31JDR8x1hgXsjc+gilrziDPteuhgORUMKQcAvrrNEjEn9w8sEQAjr/y 8irW8O+wOQXqWOkjZQ/EBLy9Po1S/nS4aIj56ItfRqphNetYDemXte1rcyBUsi5Pu6SK hDm0qqmctg2lp8mTYUtBKcrexxL2QVLXk3xWheRzWNqlTN1cHIVvXBZ2B7TBrLgV0BV2 58MkyNjdu01PE2zfuLHoiYg+X7egk1YggtPYelYf/qR5tr74+AwcjjRUu0Lg78EBW4+u fyEldueSgnDBdT4Z1ZKkIN4e1Uof80fp703JbcJ4Bz6ERV9ZyE5s1W4njrdowX2jzn7V Wirw== X-Gm-Message-State: APjAAAVJCSYEppSvqA/YCrkB641nWRLVeu9P95GWuQaVjzmT71rF0gGL /KaUd4WrOx667O9bIgK2Xu+ksw== X-Google-Smtp-Source: APXvYqzLxOM30MoA/Cs6XJMrso0FW9Y4DTwH7k8jtslzDTkT8KdRK3RB5BI+8Zi1/XhsuvNPDS2TMA== X-Received: by 2002:a5d:4090:: with SMTP id o16mr22577752wrp.292.1563789269259; Mon, 22 Jul 2019 02:54:29 -0700 (PDT) Received: from pop-os.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 91sm83158469wrp.3.2019.07.22.02.54.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jul 2019 02:54:28 -0700 (PDT) From: Alexandre Mergnat To: jbrunet@baylibre.com Cc: khilman@baylibre.com, sboyd@kernel.org, narmstrong@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, baylibre-upstreaming@groups.io, Alexandre Mergnat Subject: [PATCH 1/8] clk: meson: g12a: move clock declaration to dependency order Date: Mon, 22 Jul 2019 11:54:18 +0200 Message-Id: <20190722095425.14193-2-amergnat@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190722095425.14193-1-amergnat@baylibre.com> References: <20190722095425.14193-1-amergnat@baylibre.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This clock controller use the string comparison method to describe parent relation between the clocks. In order to migrate to clk_hw pointers, it is easier if the parent is declared before being used. This patch just move the declaration to facilitate the review of migration to the parent description method. Signed-off-by: Alexandre Mergnat --- drivers/clk/meson/g12a.c | 270 +++++++++++++++++++-------------------- 1 file changed, 135 insertions(+), 135 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 7bc5566b66f7..cbd56b2e05d0 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -257,6 +257,64 @@ static struct clk_fixed_factor g12b_sys1_pll_div16 = { }, }; +static struct clk_fixed_factor g12a_fclk_div2_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2_div", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_fclk_div2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_FIX_PLL_CNTL1, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div2_div" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor g12a_fclk_div3_div = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3_div", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_fclk_div3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_FIX_PLL_CNTL1, + .bit_idx = 20, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "fclk_div3_div" }, + .num_parents = 1, + /* + * This clock is used by the resident firmware and is required + * by the platform to operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags = CLK_IS_CRITICAL, + }, +}; + /* Datasheet names this field as "premux0" */ static struct clk_regmap g12a_cpu_clk_premux0 = { .data = &(struct clk_regmap_mux_data){ @@ -274,6 +332,23 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { }, }; +/* Datasheet names this field as "premux1" */ +static struct clk_regmap g12a_cpu_clk_premux1 = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x3, + .shift = 16, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn1_sel", + .ops = &clk_regmap_mux_ro_ops, + .parent_names = (const char *[]){ IN_PREFIX "xtal", + "fclk_div2", + "fclk_div3" }, + .num_parents = 3, + }, +}; + /* Datasheet names this field as "mux0_divn_tcnt" */ static struct clk_regmap g12a_cpu_clk_mux0_div = { .data = &(struct clk_regmap_div_data){ @@ -305,23 +380,6 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { }, }; -/* Datasheet names this field as "premux1" */ -static struct clk_regmap g12a_cpu_clk_premux1 = { - .data = &(struct clk_regmap_mux_data){ - .offset = HHI_SYS_CPU_CLK_CNTL0, - .mask = 0x3, - .shift = 16, - }, - .hw.init = &(struct clk_init_data){ - .name = "cpu_clk_dyn1_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_names = (const char *[]){ IN_PREFIX "xtal", - "fclk_div2", - "fclk_div3" }, - .num_parents = 3, - }, -}; - /* Datasheet names this field as "Mux1_divn_tcnt" */ static struct clk_regmap g12a_cpu_clk_mux1_div = { .data = &(struct clk_regmap_div_data){ @@ -1305,64 +1363,6 @@ static struct clk_regmap g12a_hdmi_pll = { }, }; -static struct clk_fixed_factor g12a_fclk_div2_div = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div2_div", - .ops = &clk_fixed_factor_ops, - .parent_names = (const char *[]){ "fixed_pll" }, - .num_parents = 1, - }, -}; - -static struct clk_regmap g12a_fclk_div2 = { - .data = &(struct clk_regmap_gate_data){ - .offset = HHI_FIX_PLL_CNTL1, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div2", - .ops = &clk_regmap_gate_ops, - .parent_names = (const char *[]){ "fclk_div2_div" }, - .num_parents = 1, - }, -}; - -static struct clk_fixed_factor g12a_fclk_div3_div = { - .mult = 1, - .div = 3, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div3_div", - .ops = &clk_fixed_factor_ops, - .parent_names = (const char *[]){ "fixed_pll" }, - .num_parents = 1, - }, -}; - -static struct clk_regmap g12a_fclk_div3 = { - .data = &(struct clk_regmap_gate_data){ - .offset = HHI_FIX_PLL_CNTL1, - .bit_idx = 20, - }, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div3", - .ops = &clk_regmap_gate_ops, - .parent_names = (const char *[]){ "fclk_div3_div" }, - .num_parents = 1, - /* - * This clock is used by the resident firmware and is required - * by the platform to operate correctly. - * Until the following condition are met, we need this clock to - * be marked as critical: - * a) Mark the clock used by a firmware resource, if possible - * b) CCF has a clock hand-off mechanism to make the sure the - * clock stays on until the proper driver comes along - */ - .flags = CLK_IS_CRITICAL, - }, -}; - static struct clk_fixed_factor g12a_fclk_div4_div = { .mult = 1, .div = 4, @@ -1900,6 +1900,66 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = { }, }; +/* Video Clocks */ + +static struct clk_regmap g12a_vid_pll_div = { + .data = &(struct meson_vid_pll_div_data){ + .val = { + .reg_off = HHI_VID_PLL_CLK_DIV, + .shift = 0, + .width = 15, + }, + .sel = { + .reg_off = HHI_VID_PLL_CLK_DIV, + .shift = 16, + .width = 2, + }, + }, + .hw.init = &(struct clk_init_data) { + .name = "vid_pll_div", + .ops = &meson_vid_pll_div_ro_ops, + .parent_names = (const char *[]){ "hdmi_pll" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, +}; + +static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div", + "hdmi_pll" }; + +static struct clk_regmap g12a_vid_pll_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VID_PLL_CLK_DIV, + .mask = 0x1, + .shift = 18, + }, + .hw.init = &(struct clk_init_data){ + .name = "vid_pll_sel", + .ops = &clk_regmap_mux_ops, + /* + * bit 18 selects from 2 possible parents: + * vid_pll_div or hdmi_pll + */ + .parent_names = g12a_vid_pll_parent_names, + .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names), + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_regmap g12a_vid_pll = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VID_PLL_CLK_DIV, + .bit_idx = 19, + }, + .hw.init = &(struct clk_init_data) { + .name = "vid_pll", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "vid_pll_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, +}; + /* VPU Clock */ static const char * const g12a_vpu_parent_names[] = { @@ -2287,66 +2347,6 @@ static struct clk_regmap g12a_vapb = { }, }; -/* Video Clocks */ - -static struct clk_regmap g12a_vid_pll_div = { - .data = &(struct meson_vid_pll_div_data){ - .val = { - .reg_off = HHI_VID_PLL_CLK_DIV, - .shift = 0, - .width = 15, - }, - .sel = { - .reg_off = HHI_VID_PLL_CLK_DIV, - .shift = 16, - .width = 2, - }, - }, - .hw.init = &(struct clk_init_data) { - .name = "vid_pll_div", - .ops = &meson_vid_pll_div_ro_ops, - .parent_names = (const char *[]){ "hdmi_pll" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - }, -}; - -static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div", - "hdmi_pll" }; - -static struct clk_regmap g12a_vid_pll_sel = { - .data = &(struct clk_regmap_mux_data){ - .offset = HHI_VID_PLL_CLK_DIV, - .mask = 0x1, - .shift = 18, - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_sel", - .ops = &clk_regmap_mux_ops, - /* - * bit 18 selects from 2 possible parents: - * vid_pll_div or hdmi_pll - */ - .parent_names = g12a_vid_pll_parent_names, - .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names), - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, - }, -}; - -static struct clk_regmap g12a_vid_pll = { - .data = &(struct clk_regmap_gate_data){ - .offset = HHI_VID_PLL_CLK_DIV, - .bit_idx = 19, - }, - .hw.init = &(struct clk_init_data) { - .name = "vid_pll", - .ops = &clk_regmap_gate_ops, - .parent_names = (const char *[]){ "vid_pll_sel" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, -}; - static const char * const g12a_vclk_parent_names[] = { "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"