From patchwork Sun Dec 29 02:59:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11311829 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 90D2E6C1 for ; Sun, 29 Dec 2019 02:59:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6D4EA21775 for ; Sun, 29 Dec 2019 02:59:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sholland.org header.i=@sholland.org header.b="LgkOV0Mb"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="Odyaqsd+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726596AbfL2C71 (ORCPT ); Sat, 28 Dec 2019 21:59:27 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:56067 "EHLO wout1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726573AbfL2C71 (ORCPT ); Sat, 28 Dec 2019 21:59:27 -0500 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id 8A301539; Sat, 28 Dec 2019 21:59:25 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Sat, 28 Dec 2019 21:59:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=ZDD1dMfJwP1vA w3RuR4Ni3oZSNxXqSku28CF47THuAw=; b=LgkOV0MbOV8eNPqF2wiRqAs4SQ49B ltrc83h6Yql5M7Wu0BWbmSPMu/vCAcDk99IFGoWqzRw0EZVFUP04gfFusaTipro+ Wp2S2iKduGZkvoShMNiXHyEw8mgD3XzstpyefuoaqHDKmJMH/6YfvPj6q2nL4Ltl hZ80Jwguo8Z+rn2jq4vk47mq/zqbJJr3IDvykrnUmdSNxQf+fqb57dyGApqqSZ6M 7sE+h+4AGcgX8O0+AUCAgyNqIxwsB973yx4Y2PD1o3jZOIk7WeeveZjL0NHsbgN+ +N7NNVMDFO3uTGFkwwvXl7qAoKwIantHVRY9s2DnAwI95mt6PS4ES7qfg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=ZDD1dMfJwP1vAw3RuR4Ni3oZSNxXqSku28CF47THuAw=; b=Odyaqsd+ h71U9919/FEsIAhGUBci826x69IhiSnMWvdCDG9Rs5VTLdBFGjANDjJS7DxnPEaf IBJDNSTaHY7Td1IDeUyjeTUlpPgZ3Tu4Y+v6+OU9N+Z3fE0aA2B3IB8412vocqsD YxMPpAv3LuEcv/56pew1E1LS8hont/voGgaEUjYMy695KSKY0DvHkZtffpCxbADN kH6IELgM884rVAGh7uU1vHBjt9xq5D4nrJazpgix5cEhkLnoXFA8Ucg9M5v2bc8R 0XuWTtcE3NZa8YcWXt3lzDb05u95pALhpekDkETIFbFcwj6MSkBqIZ/sLh1hyuW+ MKVNX/4CQ3HJEw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrvdefuddgheduucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucfkph epjedtrddufeehrddugeekrdduhedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehsrghm uhgvlhesshhhohhllhgrnhgurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd X-ME-Proxy: Received: from titanium.stl.sholland.net (70-135-148-151.lightspeed.stlsmo.sbcglobal.net [70.135.148.151]) by mail.messagingengine.com (Postfix) with ESMTPA id 4B96A3060A15; Sat, 28 Dec 2019 21:59:24 -0500 (EST) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Michael Turquette , Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Samuel Holland Subject: [PATCH 2/3] clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition Date: Sat, 28 Dec 2019 20:59:21 -0600 Message-Id: <20191229025922.46899-3-samuel@sholland.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191229025922.46899-1-samuel@sholland.org> References: <20191229025922.46899-1-samuel@sholland.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Like the APB0 clock on previous chips, this is a simple single-parent clock with an M divider. Use the equivalent helper macro instead of writing out the whole clock description manually. Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c index 45a1ed3fe674..df9c01831699 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -51,17 +51,7 @@ static struct ccu_div ar100_clk = { static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0); -static struct ccu_div r_apb1_clk = { - .div = _SUNXI_CCU_DIV(0, 2), - - .common = { - .reg = 0x00c, - .hw.init = CLK_HW_INIT("r-apb1", - "r-ahb", - &ccu_div_ops, - 0), - }, -}; +static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0); static struct ccu_div r_apb2_clk = { .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),