From patchwork Sun Dec 29 02:59:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 11311825 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C259E1395 for ; Sun, 29 Dec 2019 02:59:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B93521D7E for ; Sun, 29 Dec 2019 02:59:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sholland.org header.i=@sholland.org header.b="HfLeF8aL"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="jvpznrSy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726575AbfL2C71 (ORCPT ); Sat, 28 Dec 2019 21:59:27 -0500 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:49349 "EHLO wout1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726502AbfL2C71 (ORCPT ); Sat, 28 Dec 2019 21:59:27 -0500 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id 9057B542; Sat, 28 Dec 2019 21:59:25 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Sat, 28 Dec 2019 21:59:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=NwHOl9r2jOmJg JvC0fW2SeeCz3WaxtKWL9iSQCd7ocM=; b=HfLeF8aLCBciifaADKWL9e/+rj6Sg PL+rFqHNXg6wC61FFil1fNtmvAublyFRsjhvIc9jWkxBUzHDoyyhfRpJYbknnfvC f1/cxx3zJ9KN+BFi5s8c4s2HEHyfkfb+AF+buDN83id+hJc44N0mf8Kx2wYVtWkK gC1mw/FOtEz0xaoH2E+CyiGfm/Ggg6aQmk3RCf2smiqVXQxlb1Wiwu4ummp0qaGs naZXDP5BjTSGJh/1Dp9QQtbla980Ly9yrmoihEmtilkSLiyyH84vZuuEaVOu5DlR 4zkXNjfprV+9ym6W4IMnu4zRkDhSzIym/NnEjbk+DmM8aiR19Z6gue08g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=NwHOl9r2jOmJgJvC0fW2SeeCz3WaxtKWL9iSQCd7ocM=; b=jvpznrSy 0c1ULk1LXDfiWtqFXqygbe+vBDBQJBiWWjF69zaGmb0cE5fdwYa5dniLTFjhE8HZ bgoltdiPqQFkRE9frU/tZilhcCGOl5yKx1rwREnjbJfg26RkFEAC7SgxCuim0X9e 6t+TgbbfxQny8Wlb4VAj23jNXZkIOUFsWYgecCfZnLJsbQ6UuPyXF7P9WTH+FYn4 GS6Ao+9rHmEpG52o42xeFdzhqfOp1NoVV3EkW8x4Y3qGtK7RPuHuemBolFoKygVX QZ5LMbYxwLvaiLNPosDK6Ypes0+5Tsxm35YGgduF755o3iRQpGcKgCDVUmH/5F6n zCt+dhBGy7Guqg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrvdefuddgheduucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucfkph epjedtrddufeehrddugeekrdduhedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehsrghm uhgvlhesshhhohhllhgrnhgurdhorhhgnecuvehluhhsthgvrhfuihiivgeptd X-ME-Proxy: Received: from titanium.stl.sholland.net (70-135-148-151.lightspeed.stlsmo.sbcglobal.net [70.135.148.151]) by mail.messagingengine.com (Postfix) with ESMTPA id AC897306099E; Sat, 28 Dec 2019 21:59:24 -0500 (EST) From: Samuel Holland To: Maxime Ripard , Chen-Yu Tsai , Michael Turquette , Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Samuel Holland Subject: [PATCH 3/3] clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order Date: Sat, 28 Dec 2019 20:59:22 -0600 Message-Id: <20191229025922.46899-4-samuel@sholland.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191229025922.46899-1-samuel@sholland.org> References: <20191229025922.46899-1-samuel@sholland.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org According to the BSP source code, both the AR100 and R_APB2 clocks have PLL_PERIPH0 as mux index 3, not 2 as it was on previous chips. The pre- divider used for PLL_PERIPH0 should be changed to index 3 to match. This was verified by running a rough benchmark on the AR100 with various clock settings: | mux | pre-divider | iterations/second | clock source | |=====|=============|===================|==============| | 0 | 0 | 19033 (stable) | osc24M | | 2 | 5 | 11466 (unstable) | iosc/osc16M | | 2 | 17 | 11422 (unstable) | iosc/osc16M | | 3 | 5 | 85338 (stable) | pll-periph0 | | 3 | 17 | 27167 (stable) | pll-periph0 | The relative performance numbers all match up (with pll-periph0 running at its default 600MHz). Signed-off-by: Samuel Holland --- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c index df9c01831699..50f8d1bc7046 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -23,9 +23,9 @@ */ static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k", - "pll-periph0", "iosc" }; + "iosc", "pll-periph0" }; static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = { - { .index = 2, .shift = 0, .width = 5 }, + { .index = 3, .shift = 0, .width = 5 }, }; static struct ccu_div ar100_clk = {