diff --git a/Documentation/devicetree/bindings/clock/be,bt1-ccu-sys.yaml b/Documentation/devicetree/bindings/clock/be,bt1-ccu-sys.yaml
new file mode 100644
index 000000000000..aea09fbafc89
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/be,bt1-ccu-sys.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2019 - 2020 BAIKAL ELECTRONICS, JSC
+#
+# Baikal-T1 System Devices Clocks Control Unit Device Tree Bindings.
+#
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/be,bt1-ccu-sys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 System Devices Clock Control Unit
+
+maintainers:
+  - Serge Semin <fancer.lancer@gmail.com>
+
+description: |
+  Clocks Control Unit is the core of Baikal-T1 SoC responsible for the chip
+  subsystems clocking and resetting. The CCU is connected with an external
+  fixed rate oscillator, which signal is transformed into clocks of various
+  frequencies and then propagated to either individual IP-blocks or to groups
+  of blocks (clock domains). The transformation is done by means of an embedded
+  into CCU PLLs and gateable/non-gateable dividers. APB-bus divider register
+  provides a specific flag to initiate the full APB clock domain reset, so
+  causing each sub-device reset. Baikal-T1 CCU is logically divided into the
+  next components:
+  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
+     in general can provide any frequency supported by the CCU PLLs).
+  2) PLLs clocks generators (PLLs).
+  3) AXI-bus clock dividers (AXI).
+  4) System devices reference clock dividers (SYS) - described in this bindings
+     file.
+  which are connected with each other as shown on the next figure:
+          +---------------+
+          | Baikal-T1 CCU |
+          |   +----+------|- MIPS P5600 cores
+          | +-|PLLs|------|- DDR controller
+          | | +----+      |
+  +----+  | |  |  |       |
+  |XTAL|--|-+  |  | +---+-|
+  +----+  | |  |  +-|AXI|-|- AXI-bus
+          | |  |    +---+-|
+          | |  |          |
+          | |  +----+---+-|- APB-bus
+          | +-------|SYS|-|- Low-speed Devices
+          |         +---+-|- High-speed Devices
+          +---------------+
+  Each sub-block is represented as a separate dts-node and has an individual
+  driver to be bound with.
+
+  In order to create signals of wide range frequencies the external oscillator
+  output is primarily connected to a set of CCU PLLs. The PLLs CLKOUT is then
+  either directly connected with the corresponding clocks consumer (like P5600
+  cores or DDR controller) or passed over a CCU divider to create a signal
+  required for the clock domain. The dividers have the following structure
+          +--------------+
+  CLKIN --|->+----+ 1|\  |
+  SETCLK--|--|/DIV|->| | |
+  CLKDIV--|--|    |  | |-|->CLKLOUT
+  LOCK----|--+----+  | | |
+          |          |/  |
+          |           |  |
+  EN------|-----------+  |
+  RST-----|--------------|->RSTOUT
+          +--------------+
+  where CLKIN is the reference clock coming either from XTAL or from a CCU PLL,
+  SETCLK - a command to update the output clock in accordance with a set
+  divider, CLKDIV - clocks divider, LOCK - a signal of the output clock
+  stabilization, EN - enable/disable the divider block, RST/RSTOUT - reset
+  clocks domain signal. Depending on the consumer IP-core peculiarities the
+  dividers may lack of some functionality depicted on the figure above (like
+  EN, CLKDIV/LOCK/SETCLK or RST). In this case the corresponding clock provider
+  just doesn't expose either switching functions, or the rate configuration, or
+  both of them.
+
+  The clock dividers, which output clock is then consumed by the SoC individual
+  devices, are united into a single clocks provider called System Devices CCU.
+  The System Devices CCU dts-node uses the common clock bindings [1] with no
+  custom properties. The list of exported clocks and reset signals can be found
+  in the files: 'dt-bindings/clock/bt1-ccu.h' and
+  'dt-bindings/reset/bt1-ccu.h'.
+
+  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+allOf:
+  - $ref: /schemas/clock/clock.yaml#
+
+properties:
+  compatible:
+    const: be,bt1-ccu-sys
+
+  reg:
+    items:
+      - description: System Devices CCU sub-block base address.
+      - description: Watchdog clock divider register address in CCU.
+
+  "#clock-cells":
+    description: |
+      Clocks are referenced by the node phandle and an unique identifier
+      from 'dt-bindings/clock/bt1-ccu.h'.
+    const: 1
+
+  "#reset-cells":
+    description: |
+      CCU system devices sub-block provides a reset signal for APB and SATA
+      clock domains, which unique identifiers reside in
+      'dt-bindings/reset/bt1-ccu.h'.
+    const: 1
+
+  clocks:
+    items:
+      - description: CCU external reference clock.
+      - description: CCU SATA PLL output clock.
+      - description: CCU PCIe PLL output clock.
+      - description: CCU Ethernet PLL output clock.
+
+  clock-names:
+    items:
+      - const: ref_clk
+      - const: sata_clk
+      - const: pcie_clk
+      - const: eth_clk
+
+  clock-output-names: true
+
+  assigned-clocks: true
+
+  assigned-clock-rates: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+  - clock-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/bt1-ccu.h>
+
+    ccu_sys: ccu_sys@1F04D060 {
+      compatible = "be,bt1-ccu-sys";
+      reg = <0x1F04D060 0x0A0>,
+            <0x1F04D150 0x004>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+
+      clocks = <&osc25>,
+               <&ccu_pll CCU_SATA_PLL>,
+               <&ccu_pll CCU_PCIE_PLL>,
+               <&ccu_pll CCU_ETH_PLL>;
+      clock-names = "ref_clk", "sata_clk", "pcie_clk",
+                    "eth_clk";
+
+      clock-output-names = "sys_sata_ref_clk", "sys_apb_clk",
+                           "sys_gmac0_csr_clk", "sys_gmac0_tx_clk",
+                           "sys_gmac0_ptp_clk", "sys_gmac1_csr_clk",
+                           "sys_gmac1_tx_clk", "sys_gmac1_ptp_clk",
+                           "sys_xgmac_ref_clk", "sys_xgmac_ptp_clk",
+                           "sys_usb_clk", "sys_pvt_clk",
+                           "sys_hwa_clk", "sys_uart_clk",
+                           "sys_spi_clk", "sys_i2c1_clk",
+                           "sys_i2c2_clk", "sys_gpio_clk",
+                           "sys_timer0_clk", "sys_timer1_clk",
+                           "sys_timer2_clk", "sys_wdt_clk";
+      };
+...
diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h
index ebe723c6e0a8..4dcad1eb721f 100644
--- a/include/dt-bindings/clock/bt1-ccu.h
+++ b/include/dt-bindings/clock/bt1-ccu.h
@@ -27,4 +27,28 @@
 #define CCU_AXI_HWA_CLK			9
 #define CCU_AXI_SRAM_CLK		10
 
+/* Baikal-T1 System Devices CCU Clocks indeces. */
+#define CCU_SYS_SATA_REF_CLK		0
+#define CCU_SYS_APB_CLK			1
+#define CCU_SYS_GMAC0_CSR_CLK		2
+#define CCU_SYS_GMAC0_TX_CLK		3
+#define CCU_SYS_GMAC0_PTP_CLK		4
+#define CCU_SYS_GMAC1_CSR_CLK		5
+#define CCU_SYS_GMAC1_TX_CLK		6
+#define CCU_SYS_GMAC1_PTP_CLK		7
+#define CCU_SYS_XGMAC_REF_CLK		8
+#define CCU_SYS_XGMAC_PTP_CLK		9
+#define CCU_SYS_USB_CLK			10
+#define CCU_SYS_PVT_CLK			11
+#define CCU_SYS_HWA_CLK			12
+#define CCU_SYS_UART_CLK		13
+#define CCU_SYS_SPI_CLK			14
+#define CCU_SYS_I2C1_CLK		15
+#define CCU_SYS_I2C2_CLK		16
+#define CCU_SYS_GPIO_CLK		17
+#define CCU_SYS_TIMER0_CLK		18
+#define CCU_SYS_TIMER1_CLK		19
+#define CCU_SYS_TIMER2_CLK		20
+#define CCU_SYS_WDT_CLK			21
+
 #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
diff --git a/include/dt-bindings/reset/bt1-ccu.h b/include/dt-bindings/reset/bt1-ccu.h
index 4de5b6bcd433..0bd8fd0edb41 100644
--- a/include/dt-bindings/reset/bt1-ccu.h
+++ b/include/dt-bindings/reset/bt1-ccu.h
@@ -20,4 +20,8 @@
 #define CCU_AXI_HWA_RST			9
 #define CCU_AXI_SRAM_RST		10
 
+/* Baikal-T1 System Devices CCU Reset indeces. */
+#define CCU_SYS_SATA_REF_RST		0
+#define CCU_SYS_APB_RST			1
+
 #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */
