From patchwork Tue Mar 17 16:10:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11443303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1EE151392 for ; Tue, 17 Mar 2020 16:10:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F38442075E for ; Tue, 17 Mar 2020 16:10:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584461431; bh=sMXNasHzye75V2ttAQ5Wlh02bP+5GG5y8R/UY0ueBkY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=U0Ue9O/zRGxfx2aUID/YpvkjEiE40trpWe8VlAZMKo1cAPElh96Piju3aXbMgTq1Q lDQOiOLhZ8/A4xA6WJHxa3M6Od0EiRiFkUV+OqHKJ9zngoGRqJGTodR77jsZ7e6N6H HpZt7/g/Y/5FqGCck7mcJyglfJyasV9fdMFM5hgY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726808AbgCQQKa (ORCPT ); Tue, 17 Mar 2020 12:10:30 -0400 Received: from mail.kernel.org ([198.145.29.99]:35928 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726016AbgCQQK3 (ORCPT ); Tue, 17 Mar 2020 12:10:29 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 84C9920757; Tue, 17 Mar 2020 16:10:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584461429; bh=sMXNasHzye75V2ttAQ5Wlh02bP+5GG5y8R/UY0ueBkY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zS41GxBz5uG3eWw9b7ECjw5MPBAmQei1MfBtRUpgGq6yJyVl9h2baFlSV4AWvVDvB ifUHryvjHoMLWQIP4wIfgD8URoobpePjJn8NV6TzUZIvIn2Sf+jJZen8PrjZzQmIA2 Lt0hZZrD/2hB44lXewOaWkQKqB3E77JuyCFaeov4= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, Dinh Nguyen Subject: [PATCH 2/5] clk: socfpga: remove clk_ops enable/disable methods Date: Tue, 17 Mar 2020 11:10:19 -0500 Message-Id: <20200317161022.11181-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200317161022.11181-1-dinguyen@kernel.org> References: <20200317161022.11181-1-dinguyen@kernel.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Dinh Nguyen The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-pll-a10.c | 2 -- drivers/clk/socfpga/clk-pll-s10.c | 2 -- drivers/clk/socfpga/clk-pll.c | 2 -- 3 files changed, 6 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 3816fc04b274..6d9395106c0c 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) { diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index bcd3f14e9145..9faa80ff3b53 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) { diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index dc65cc0fd3bd..a001641b2f42 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) {