Message ID | 20200330021640.14133-1-zhang.lyra@gmail.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | clk: sprd: fix to get a correct ibias of pll | expand |
Quoting Chunyan Zhang (2020-03-29 19:16:40) > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > The current driver is getting a wrong ibias index of pll clocks from > number 1. This patch fix that issue, then getting ibias index from 0. > > Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support") > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> > --- Applied to clk-next
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c index 640270f51aa5..15791484388f 100644 --- a/drivers/clk/sprd/pll.c +++ b/drivers/clk/sprd/pll.c @@ -87,11 +87,12 @@ static u32 pll_get_ibias(u64 rate, const u64 *table) { u32 i, num = table[0]; - for (i = 1; i < num + 1; i++) - if (rate <= table[i]) + /* table[0] indicates the number of items in this table */ + for (i = 0; i < num; i++) + if (rate <= table[i + 1]) break; - return (i == num + 1) ? num : i; + return i == num ? num - 1 : i; } static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,