| Message ID | 20200330221104.3163788-4-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | RFC, archived |
| Headers | show |
| Series | GPU DVFS for Meson GXBB/GXL/GXM/G12A/G12B/SM1 | expand |
Hi, On 31/03/2020 00:11, Martin Blumenstingl wrote: > Add the OPP table for the Mali-450 GPU and drop the hardcoded initial > clock configuration. This enables GPU DVFS and thus saves power when the > GPU is not in use while still being able switch to a higher clock on > demand. > > While here, make most of meson-gxl-mali re-usable to reduce the amount > of duplicate code between GXBB and GXL. This is more important now as we > don't want to duplicate the GPU OPP table. Looks good, but please add comment about the CLKID_GP0_PLL assigned clock rate. I'll ask LibreELEC people to have a run on these patches (including the clk changes) with Kodi. Neil > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > .../boot/dts/amlogic/meson-gx-mali450.dtsi | 61 +++++++++++++++++++ > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 51 ++++------------ > .../boot/dts/amlogic/meson-gxl-mali.dtsi | 46 +++----------- > 3 files changed, 81 insertions(+), 77 deletions(-) > create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi > > diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi > new file mode 100644 > index 000000000000..f9771b51c852 > --- /dev/null > +++ b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi > @@ -0,0 +1,61 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2017 BayLibre SAS > + * Author: Neil Armstrong <narmstrong@baylibre.com> > + */ > + > +/ { > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-125000000 { > + opp-hz = /bits/ 64 <125000000>; > + opp-microvolt = <950000>; > + }; > + opp-250000000 { > + opp-hz = /bits/ 64 <250000000>; > + opp-microvolt = <950000>; > + }; > + opp-285714285 { > + opp-hz = /bits/ 64 <285714285>; > + opp-microvolt = <950000>; > + }; > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + opp-microvolt = <950000>; > + }; > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-microvolt = <950000>; > + }; > + opp-666666666 { > + opp-hz = /bits/ 64 <666666666>; > + opp-microvolt = <950000>; > + }; > + opp-744000000 { > + opp-hz = /bits/ 64 <744000000>; > + opp-microvolt = <950000>; > + }; > + }; > +}; > + > +&apb { > + mali: gpu@c0000 { > + compatible = "arm,mali-450"; > + reg = <0x0 0xc0000 0x0 0x40000>; > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gp", "gpmmu", "pp", "pmu", > + "pp0", "ppmmu0", "pp1", "ppmmu1", > + "pp2", "ppmmu2"; > + operating-points-v2 = <&gpu_opp_table>; > + }; > +}; > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > index 0cb40326b0d3..e43b330129c7 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > @@ -4,6 +4,7 @@ > */ > > #include "meson-gx.dtsi" > +#include "meson-gx-mali450.dtsi" > #include <dt-bindings/gpio/meson-gxbb-gpio.h> > #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> > #include <dt-bindings/clock/gxbb-clkc.h> > @@ -241,46 +242,6 @@ mux { > }; > }; > > -&apb { > - mali: gpu@c0000 { > - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; > - reg = <0x0 0xc0000 0x0 0x40000>; > - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "gp", "gpmmu", "pp", "pmu", > - "pp0", "ppmmu0", "pp1", "ppmmu1", > - "pp2", "ppmmu2"; > - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; > - clock-names = "bus", "core"; > - > - /* > - * Mali clocking is provided by two identical clock paths > - * MALI_0 and MALI_1 muxed to a single clock by a glitch > - * free mux to safely change frequency while running. > - */ > - assigned-clocks = <&clkc CLKID_GP0_PLL>, > - <&clkc CLKID_MALI_0_SEL>, > - <&clkc CLKID_MALI_0>, > - <&clkc CLKID_MALI>; /* Glitch free mux */ > - assigned-clock-parents = <0>, /* Do Nothing */ > - <&clkc CLKID_GP0_PLL>, > - <0>, /* Do Nothing */ > - <&clkc CLKID_MALI_0>; > - assigned-clock-rates = <744000000>, > - <0>, /* Do Nothing */ > - <744000000>, > - <0>; /* Do Nothing */ > - }; > -}; > - > &cbus { > spifc: spi@8c80 { > compatible = "amlogic,meson-gxbb-spifc"; > @@ -362,6 +323,16 @@ &i2c_C { > clocks = <&clkc CLKID_I2C>; > }; > > +&mali { > + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; > + > + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; > + clock-names = "bus", "core"; > + > + assigned-clocks = <&clkc CLKID_GP0_PLL>; > + assigned-clock-rates = <744000000>; > +}; > + > &periphs { > pinctrl_periphs: pinctrl@4b0 { > compatible = "amlogic,meson-gxbb-periphs-pinctrl"; > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi > index 6aaafff674f9..478e755cc87c 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi > @@ -4,42 +4,14 @@ > * Author: Neil Armstrong <narmstrong@baylibre.com> > */ > > -&apb { > - mali: gpu@c0000 { > - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; > - reg = <0x0 0xc0000 0x0 0x40000>; > - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "gp", "gpmmu", "pp", "pmu", > - "pp0", "ppmmu0", "pp1", "ppmmu1", > - "pp2", "ppmmu2"; > - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; > - clock-names = "bus", "core"; > +#include "meson-gx-mali450.dtsi" > > - /* > - * Mali clocking is provided by two identical clock paths > - * MALI_0 and MALI_1 muxed to a single clock by a glitch > - * free mux to safely change frequency while running. > - */ > - assigned-clocks = <&clkc CLKID_GP0_PLL>, > - <&clkc CLKID_MALI_0_SEL>, > - <&clkc CLKID_MALI_0>, > - <&clkc CLKID_MALI>; /* Glitch free mux */ > - assigned-clock-parents = <0>, /* Do Nothing */ > - <&clkc CLKID_GP0_PLL>, > - <0>, /* Do Nothing */ > - <&clkc CLKID_MALI_0>; > - assigned-clock-rates = <744000000>, > - <0>, /* Do Nothing */ > - <744000000>, > - <0>; /* Do Nothing */ > - }; > +&mali { > + compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; > + > + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; > + clock-names = "bus", "core"; > + > + assigned-clocks = <&clkc CLKID_GP0_PLL>; > + assigned-clock-rates = <744000000>; > }; >
Hi Neil, On Tue, Mar 31, 2020 at 9:44 AM Neil Armstrong <narmstrong@baylibre.com> wrote: > > Hi, > > On 31/03/2020 00:11, Martin Blumenstingl wrote: > > Add the OPP table for the Mali-450 GPU and drop the hardcoded initial > > clock configuration. This enables GPU DVFS and thus saves power when the > > GPU is not in use while still being able switch to a higher clock on > > demand. > > > > While here, make most of meson-gxl-mali re-usable to reduce the amount > > of duplicate code between GXBB and GXL. This is more important now as we > > don't want to duplicate the GPU OPP table. > > Looks good, but please add comment about the CLKID_GP0_PLL assigned clock rate. I can do that - do you want that comment to be part of the patch description or in the .dtsi? > I'll ask LibreELEC people to have a run on these patches (including the clk changes) with Kodi. real-world testing would be amazing! Martin
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi new file mode 100644 index 000000000000..f9771b51c852 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/ { + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <950000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <950000>; + }; + opp-285714285 { + opp-hz = /bits/ 64 <285714285>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + }; + opp-666666666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <950000>; + }; + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-microvolt = <950000>; + }; + }; +}; + +&apb { + mali: gpu@c0000 { + compatible = "arm,mali-450"; + reg = <0x0 0xc0000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + operating-points-v2 = <&gpu_opp_table>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 0cb40326b0d3..e43b330129c7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -4,6 +4,7 @@ */ #include "meson-gx.dtsi" +#include "meson-gx-mali450.dtsi" #include <dt-bindings/gpio/meson-gxbb-gpio.h> #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> #include <dt-bindings/clock/gxbb-clkc.h> @@ -241,46 +242,6 @@ mux { }; }; -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; -}; - &cbus { spifc: spi@8c80 { compatible = "amlogic,meson-gxbb-spifc"; @@ -362,6 +323,16 @@ &i2c_C { clocks = <&clkc CLKID_I2C>; }; +&mali { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_GP0_PLL>; + assigned-clock-rates = <744000000>; +}; + &periphs { pinctrl_periphs: pinctrl@4b0 { compatible = "amlogic,meson-gxbb-periphs-pinctrl"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi index 6aaafff674f9..478e755cc87c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi @@ -4,42 +4,14 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; +#include "meson-gx-mali450.dtsi" - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; +&mali { + compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_GP0_PLL>; + assigned-clock-rates = <744000000>; };
Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. While here, make most of meson-gxl-mali re-usable to reduce the amount of duplicate code between GXBB and GXL. This is more important now as we don't want to duplicate the GPU OPP table. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- .../boot/dts/amlogic/meson-gx-mali450.dtsi | 61 +++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 51 ++++------------ .../boot/dts/amlogic/meson-gxl-mali.dtsi | 46 +++----------- 3 files changed, 81 insertions(+), 77 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi