diff mbox series

[v5.7] clk: tegra: Fix initial rate for pll_a on Tegra124

Message ID 20200505071655.644773-1-thierry.reding@gmail.com (mailing list archive)
State Accepted, archived
Headers show
Series [v5.7] clk: tegra: Fix initial rate for pll_a on Tegra124 | expand

Commit Message

Thierry Reding May 5, 2020, 7:16 a.m. UTC 
From: Thierry Reding <treding@nvidia.com>

pll_a_out0 and the I2S clocks are already configured to default to rates
corresponding to a 44.1 kHz sampling rate, but the pll_a configuration
was set to a default that is not listed in the frequency table, which
caused the PLL code to compute an invalid configuration. As a result of
this invalid configuration, Jetson TK1 fails to resume from suspend.

This used to get papered over because the ASoC driver would force audio
clocks to a 44.1 kHz configuration on boot. However, that's not really
necessary and was hence removed in commit ff5d18cb04f4 ("ASoC: tegra:
Enable audio mclk during tegra_asoc_utils_init()").

Fix the initial rate for pll_a so that it matches the 44.1 kHz entry in
the pll_a frequency table.

Fixes: ff5d18cb04f4 ("ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init()")
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Mike, Stephen,

this fixes a regression in v5.7, so it'd be great if you could queue it
up in your fixes branch.

Thanks,
Thierry

 drivers/clk/tegra/clk-tegra124.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Stephen Boyd May 12, 2020, 11:26 p.m. UTC | #1 
Quoting Thierry Reding (2020-05-05 00:16:55)
> From: Thierry Reding <treding@nvidia.com>
> 
> pll_a_out0 and the I2S clocks are already configured to default to rates
> corresponding to a 44.1 kHz sampling rate, but the pll_a configuration
> was set to a default that is not listed in the frequency table, which
> caused the PLL code to compute an invalid configuration. As a result of
> this invalid configuration, Jetson TK1 fails to resume from suspend.
> 
> This used to get papered over because the ASoC driver would force audio
> clocks to a 44.1 kHz configuration on boot. However, that's not really
> necessary and was hence removed in commit ff5d18cb04f4 ("ASoC: tegra:
> Enable audio mclk during tegra_asoc_utils_init()").
> 
> Fix the initial rate for pll_a so that it matches the 44.1 kHz entry in
> the pll_a frequency table.
> 
> Fixes: ff5d18cb04f4 ("ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init()")
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---

Applied to clk-fixes
diff mbox series

Patch

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 64e229ddf2a5..e931319dcc9d 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1292,7 +1292,7 @@  static struct tegra_clk_init_table common_init_table[] __initdata = {
 	{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
-	{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 0 },
+	{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 282240000, 0 },
 	{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
 	{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },