From patchwork Mon May 11 19:25:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lubomir Rintel X-Patchwork-Id: 11541571 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 47EAB15E6 for ; Mon, 11 May 2020 19:25:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39C3B2075E for ; Mon, 11 May 2020 19:25:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731535AbgEKTZi (ORCPT ); Mon, 11 May 2020 15:25:38 -0400 Received: from v6.sk ([167.172.42.174]:52376 "EHLO v6.sk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731515AbgEKTZi (ORCPT ); Mon, 11 May 2020 15:25:38 -0400 Received: from localhost (v6.sk [IPv6:::1]) by v6.sk (Postfix) with ESMTP id C5699610CF; Mon, 11 May 2020 19:25:36 +0000 (UTC) From: Lubomir Rintel To: Michael Turquette Cc: Stephen Boyd , Rob Herring , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lubomir Rintel Subject: [PATCH v2 06/10] clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init() Date: Mon, 11 May 2020 21:25:13 +0200 Message-Id: <20200511192517.1206442-7-lkundrak@v3.sk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200511192517.1206442-1-lkundrak@v3.sk> References: <20200511192517.1206442-1-lkundrak@v3.sk> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is a trivial rename for a routine that registers more clock sources than the PLLs -- there's also a XO. Signed-off-by: Lubomir Rintel --- drivers/clk/mmp/clk-of-mmp2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index 524574187c17..ac88ea99b7c6 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -139,7 +139,7 @@ static struct mmp_clk_factor_tbl uart_factor_tbl[] = { {.num = 3521, .den = 689}, /*19.23MHZ */ }; -static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit) +static void mmp2_main_clk_init(struct mmp2_clk_unit *pxa_unit) { struct clk *clk; struct mmp_clk_unit *unit = &pxa_unit->unit; @@ -456,7 +456,7 @@ static void __init mmp2_clk_init(struct device_node *np) mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS); - mmp2_pll_init(pxa_unit); + mmp2_main_clk_init(pxa_unit); mmp2_apb_periph_clk_init(pxa_unit);