From patchwork Wed May 27 05:36:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11571891 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3707790 for ; Wed, 27 May 2020 05:37:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1AE51208DB for ; Wed, 27 May 2020 05:37:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aE6EHnMD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725379AbgE0Fg7 (ORCPT ); Wed, 27 May 2020 01:36:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725265AbgE0Fg7 (ORCPT ); Wed, 27 May 2020 01:36:59 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32281C061A0F; Tue, 26 May 2020 22:36:59 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id x13so11324621pfn.11; Tue, 26 May 2020 22:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Uwxa46CvTM5ECW30BkNGZjhjXbVyQcR87+DO9oGqllg=; b=aE6EHnMDX0JmXCER9fDCEscMHHLDDsA6R8dZthc158qDWpdhrVsngKgncts3+asDmM aoedTuUdhSySOOujiix+w+/hWay3IfsuGWPDpq0wDP5NIInlZY0y1ibj//519/cbkd4f ONncQAroZ/yjSExwCYRFnUpuf55InNb6KhQGKTGTOA9a2oQxRau2SnLPgkz6dz0E1bTj S7p234icghEOr7f9d2uhApNiw/4x6qrMp7HZWpYXkny2LNY93If1pzY4/qAOkDlY5/3F UizXy/Y9uwBkEdWdoTrIPZOIlipaEd9RaA6yjELdpqmYG+GYNZpj4o7FTNkeOqP5qUy/ hQ1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Uwxa46CvTM5ECW30BkNGZjhjXbVyQcR87+DO9oGqllg=; b=qnGenva9KYBdPOlR8WsCgViwIAUNzV5Yra+nfjV1T9V/VsDF6tbLNePHApu+Dn4d+6 7kddEcNSvYUBSoCTiR3IUugexeGAmlpp5K6VRm1BpmKF9//ehBrRv1nXt+EFd1GLNzfg uLXoQjJTFg0k6X7JnhX4tv4b1Do065svbMRdYVtyaz4eiqByO9MhTdvywLrYI74IBEiK DnX2IscLvf/3lfsJSwZsNM//wgPJQBEpBZRUwB5s2fNafEzq1LmJ6pESrCxkbRmG3Pp3 WUjnp2/or1g56rP3SRa0IyP6ArbaAbf/KSHDzzlYhhMfUsfWy7i+inOOEp2Vj3U4LvjO ueEQ== X-Gm-Message-State: AOAM5333uiPewiBC7vHNvaRUeFL0G1pVd4VLQydwP5CYnRxNrSaJOQ7z 70dEq7PSEazKiC6eWTr0/+4= X-Google-Smtp-Source: ABdhPJxqytUB8SfBGZSchfvYEIX2fWnykNTsva1POvkE4JkhGNDXruBrvH15uiFtHv26S0jwqUBfXQ== X-Received: by 2002:a63:214d:: with SMTP id s13mr2233129pgm.277.1590557818829; Tue, 26 May 2020 22:36:58 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id r34sm1092406pgl.38.2020.05.26.22.36.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2020 22:36:58 -0700 (PDT) From: Chunyan Zhang To: Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [RESEND PATCH v2 1/4] clk: sprd: check its parent status before reading gate clock Date: Wed, 27 May 2020 13:36:35 +0800 Message-Id: <20200527053638.31439-2-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200527053638.31439-1-zhang.lyra@gmail.com> References: <20200527053638.31439-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Chunyan Zhang Some clocks only can be accessed if their parent is enabled. mipi_csi_xx clocks on SC9863A are an examples. We have to ensure the parent clock is enabled when reading those clocks. Signed-off-by: Chunyan Zhang --- drivers/clk/sprd/gate.c | 7 +++++++ drivers/clk/sprd/gate.h | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c index 574cfc116bbc..56e1714b541e 100644 --- a/drivers/clk/sprd/gate.c +++ b/drivers/clk/sprd/gate.c @@ -94,8 +94,15 @@ static int sprd_gate_is_enabled(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); struct sprd_clk_common *common = &sg->common; + struct clk_hw *parent; unsigned int reg; + if (sg->flags & SPRD_GATE_NON_AON) { + parent = clk_hw_get_parent(hw); + if (!parent || !clk_hw_is_enabled(parent)) + return 0; + } + regmap_read(common->regmap, common->reg, ®); if (sg->flags & CLK_GATE_SET_TO_DISABLE) diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h index b55817869367..e738dafa4fe9 100644 --- a/drivers/clk/sprd/gate.h +++ b/drivers/clk/sprd/gate.h @@ -19,6 +19,15 @@ struct sprd_gate { struct sprd_clk_common common; }; +/* + * sprd_gate->flags is used for: + * CLK_GATE_SET_TO_DISABLE BIT(0) + * CLK_GATE_HIWORD_MASK BIT(1) + * CLK_GATE_BIG_ENDIAN BIT(2) + * so we define new flags from BIT(3) + */ +#define SPRD_GATE_NON_AON BIT(3) /* not alway powered on, check before read */ + #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ _sc_offset, _enable_mask, _flags, \ _gate_flags, _udelay, _ops, _fn) \