From patchwork Wed May 27 05:36:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11571895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6BD9A912 for ; Wed, 27 May 2020 05:37:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5348B207ED for ; Wed, 27 May 2020 05:37:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MUC+ktwX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726214AbgE0FhK (ORCPT ); Wed, 27 May 2020 01:37:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726209AbgE0FhJ (ORCPT ); Wed, 27 May 2020 01:37:09 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F251BC061A0F; Tue, 26 May 2020 22:37:08 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id m7so9733730plt.5; Tue, 26 May 2020 22:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cqkf7LycevmgLpVmZeBhW8pIulT8kk5Dc9E7315h7UE=; b=MUC+ktwXiZmTf+GNJYOcuArbLORoC4bO3Seb9eAiMiZiNcB4OH6xtny+LZIddrpyUO e7T9adWN134UIMYOMwA64KOWAzer6xMCAWSUn6bAeg/7RKofNjaVAtLx2ecAZ5XsrerW mBkecyDGJL0wztKLTWXMJ3dvDLYBZwIlBspQsUgGYTVCFcSfa8uglMJ7oszoDbTmXM3b lZ2jfO5C/JkDJ1K9S0g9NCoY5LgJ7vvSDaojNtXog9gNbEqEyZ90dNnlfyTj5xlMfcZ6 DTzwLv5NyeltsWNX3RQMg/axB3GCl3jGo7qjZg8zNz71hv2ArFIOsI/PSdJSuI/sD22r 1uIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cqkf7LycevmgLpVmZeBhW8pIulT8kk5Dc9E7315h7UE=; b=TTZCYDpl3QfsKXSpGJ3SDD8zKMh4EnST8X8lWQ1PXKp1+gfY6ItAlG8G2FFTUPSphV O7u8HzDKjzGCDoY7AC+Zq/IqKzXaNlComn8cA0YKRWVEwfloESGlvNQwmts89dRNXZvf /4d0bDICz79BuZVc2jgJq3FNwGkpsOaxzu3xzLVJPc2eUB14SBMG5gkuS4CawexMqqLA TV4rRpeFpM2tRwI4e9+8wgARpPWLhPFT98/xbKHaZbygSmsUtynBknpemp0G5UVwi3su OPZXaEruwoOhYgQIRAitRpTe/pWidSoaaBN0UkGE9bumkEpNZJELqzO/fueEQNqozcoC IaKg== X-Gm-Message-State: AOAM5332bziG6v81hGOqNfsJpLiiW8wq/74KqTwagDwnkOYWoJcWtS5M mIfJWXKmb5QBExg/pQ+X4Jc= X-Google-Smtp-Source: ABdhPJy8K1WVcQM1HCK6TVkGYFSMk0D4eOQMyBO8IUfUJoEQH8Ney49GrcU3NPF9ePs8Y2CRZsSwPQ== X-Received: by 2002:a17:90b:a13:: with SMTP id gg19mr3070516pjb.49.1590557828509; Tue, 26 May 2020 22:37:08 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id r34sm1092406pgl.38.2020.05.26.22.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2020 22:37:07 -0700 (PDT) From: Chunyan Zhang To: Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [RESEND PATCH v2 4/4] clk: sprd: add mipi_csi_xx gate clocks Date: Wed, 27 May 2020 13:36:38 +0800 Message-Id: <20200527053638.31439-5-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200527053638.31439-1-zhang.lyra@gmail.com> References: <20200527053638.31439-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Chunyan Zhang mipi_csi_xx clocks are used by camera sensors. Signed-off-by: Chunyan Zhang --- drivers/clk/sprd/sc9863a-clk.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/sprd/sc9863a-clk.c b/drivers/clk/sprd/sc9863a-clk.c index a0631f7756cf..f67bd08f225c 100644 --- a/drivers/clk/sprd/sc9863a-clk.c +++ b/drivers/clk/sprd/sc9863a-clk.c @@ -1615,6 +1615,36 @@ static const struct sprd_clk_desc sc9863a_mm_gate_desc = { .hw_clks = &sc9863a_mm_gate_hws, }; +/* camera sensor clocks */ +static SPRD_GATE_CLK_HW(mipi_csi_clk, "mipi-csi-clk", &mahb_ckg_eb.common.hw, + 0x20, BIT(16), 0, SPRD_GATE_NON_AON); +static SPRD_GATE_CLK_HW(mipi_csi_s_clk, "mipi-csi-s-clk", &mahb_ckg_eb.common.hw, + 0x24, BIT(16), 0, SPRD_GATE_NON_AON); +static SPRD_GATE_CLK_HW(mipi_csi_m_clk, "mipi-csi-m-clk", &mahb_ckg_eb.common.hw, + 0x28, BIT(16), 0, SPRD_GATE_NON_AON); + +static struct sprd_clk_common *sc9863a_mm_clk_clks[] = { + /* address base is 0x60900000 */ + &mipi_csi_clk.common, + &mipi_csi_s_clk.common, + &mipi_csi_m_clk.common, +}; + +static struct clk_hw_onecell_data sc9863a_mm_clk_hws = { + .hws = { + [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, + [CLK_MIPI_CSI_S] = &mipi_csi_s_clk.common.hw, + [CLK_MIPI_CSI_M] = &mipi_csi_m_clk.common.hw, + }, + .num = CLK_MM_CLK_NUM, +}; + +static const struct sprd_clk_desc sc9863a_mm_clk_desc = { + .clk_clks = sc9863a_mm_clk_clks, + .num_clk_clks = ARRAY_SIZE(sc9863a_mm_clk_clks), + .hw_clks = &sc9863a_mm_clk_hws, +}; + static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m", 0x0, @@ -1737,6 +1767,8 @@ static const struct of_device_id sprd_sc9863a_clk_ids[] = { .data = &sc9863a_aonapb_gate_desc }, { .compatible = "sprd,sc9863a-mm-gate", /* 0x60800000 */ .data = &sc9863a_mm_gate_desc }, + { .compatible = "sprd,sc9863a-mm-clk", /* 0x60900000 */ + .data = &sc9863a_mm_clk_desc }, { .compatible = "sprd,sc9863a-apapb-gate", /* 0x71300000 */ .data = &sc9863a_apapb_gate_desc }, { }