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[217.229.16.121]) by smtp.gmail.com with ESMTPSA id s18sm1044789edi.45.2020.06.03.04.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2020 04:19:29 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Michael Turquette , Stephen Boyd , Jon Hunter , LABBE Corentin , Dmitry Osipenko , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 2/2] clk: tegra: Always program PLL_E when enabled Date: Wed, 3 Jun 2020 13:19:23 +0200 Message-Id: <20200603111923.3545261-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200603111923.3545261-1-thierry.reding@gmail.com> References: <20200603111923.3545261-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Thierry Reding Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") added checks to avoid enabling PLLs that have already been enabled by the bootloader. However, the PLL_E configuration inherited from the bootloader isn't necessarily the one that is needed for the kernel. This can cause SATA to fail like this: [ 5.310270] phy phy-sata.6: phy poweron failed --> -110 [ 5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110 [ 5.323022] tegra-ahci: probe of 70027000.sata failed with error -110 Fix this by always programming the PLL_E. This ensures that any mis- configuration by the bootloader will be overwritten by the kernel. Fixes: bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") Reported-by: LABBE Corentin Signed-off-by: Thierry Reding Tested-by: Corentin Labbe Reviewed-by: Dmitry Osipenko Acked-by: Stephen Boyd --- drivers/clk/tegra/clk-pll.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 583d2ac61e9e..b2d39a66f0fa 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1601,9 +1601,6 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) unsigned long flags = 0; unsigned long input_rate; - if (clk_pll_is_enabled(hw)) - return 0; - input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))