| Message ID | 20210104132806.720558-3-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: meson8b: video clock tree updates | expand |
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index f8bd211db720..16ab595ab1a4 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3781,6 +3781,11 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } + /* The HDMI PLL VCO is limited to 1.2G~3.0GHz */ + clk_hw_set_rate_range(clk_hw_onecell_data->hws[CLKID_HDMI_PLL_DCO], + 1200 * 1000UL * 1000UL, + 3000 * 1000UL * 1000UL); + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_onecell_data); if (ret)
According to the public S805 datasheet the HDMI PLL VCO frequency has to be between 1.2GHz and 3.0GHz. Add this range in our driver so we won't get too low (which means the PLL won't lock) or too high. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 5 +++++ 1 file changed, 5 insertions(+)