| Message ID | 20210313021919.435332-9-konrad.dybcio@somainline.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver | expand |
On Sat, Mar 13, 2021 at 03:19:18AM +0100, Konrad Dybcio wrote: > Some devices come with a different SDCC clock configuration, > account for that. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > .../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++ > drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml > index f8067fb1bbd6..9db0800a4ee4 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml > @@ -49,6 +49,10 @@ properties: > description: > Protected clock specifier list as per common clock binding. > > + qcom,sdcc2-clk-src-40mhz: > + description: SDCC2_APPS clock source runs at 40MHz. > + type: boolean Why don't you have some input clock you can get the rate from? > + > required: > - compatible > - reg
On 24.03.2021 18:11, Rob Herring wrote: > On Sat, Mar 13, 2021 at 03:19:18AM +0100, Konrad Dybcio wrote: >> Some devices come with a different SDCC clock configuration, >> account for that. >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> --- >> .../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++ >> drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++ >> 2 files changed, 20 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml >> index f8067fb1bbd6..9db0800a4ee4 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml >> @@ -49,6 +49,10 @@ properties: >> description: >> Protected clock specifier list as per common clock binding. >> >> + qcom,sdcc2-clk-src-40mhz: >> + description: SDCC2_APPS clock source runs at 40MHz. >> + type: boolean > Why don't you have some input clock you can get the rate from? This is a SONY-custom hardware change and that's as much information as I can get. Schematics are not available and it's solely based on the downstream kernel source. Konrad
Quoting Konrad Dybcio (2021-03-24 10:12:34) > > On 24.03.2021 18:11, Rob Herring wrote: > > On Sat, Mar 13, 2021 at 03:19:18AM +0100, Konrad Dybcio wrote: > >> Some devices come with a different SDCC clock configuration, > >> account for that. > >> > >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > >> --- > >> .../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++ > >> drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++ > >> 2 files changed, 20 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml > >> index f8067fb1bbd6..9db0800a4ee4 100644 > >> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml > >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml > >> @@ -49,6 +49,10 @@ properties: > >> description: > >> Protected clock specifier list as per common clock binding. > >> > >> + qcom,sdcc2-clk-src-40mhz: > >> + description: SDCC2_APPS clock source runs at 40MHz. > >> + type: boolean > > Why don't you have some input clock you can get the rate from? > > > This is a SONY-custom hardware change and that's as much information as I can get. Schematics are not available and it's solely based on the downstream kernel source. > Presumably we can add the extra frequencies to the frequency plan array and not need this extra property in DT. The consumer driver should be able to pick the correct frequency.
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml index f8067fb1bbd6..9db0800a4ee4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -49,6 +49,10 @@ properties: description: Protected clock specifier list as per common clock binding. + qcom,sdcc2-clk-src-40mhz: + description: SDCC2_APPS clock source runs at 40MHz. + type: boolean + required: - compatible - reg diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index a5b9db7678d1..1fbbf5f5dee0 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -1018,6 +1018,19 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { }, }; +static struct freq_tbl ftbl_sdcc2_40mhz_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 15, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(40000000, P_GPLL0, 15, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(80000000, P_GPLL0, 7.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(200000000, P_GPLL0, 3, 0, 0), + { } +}; + static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { F(144000, P_XO, 16, 3, 25), F(400000, P_XO, 12, 1, 4), @@ -2793,6 +2806,9 @@ static int gcc_msm8994_probe(struct platform_device *pdev) blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; } + if (of_find_property(dev->of_node, "qcom,sdcc2-clk-src-40mhz", NULL)) + sdcc2_apps_clk_src.freq_tbl = ftbl_sdcc2_40mhz_apps_clk_src; + return qcom_cc_probe(pdev, &gcc_msm8994_desc); }
Some devices come with a different SDCC clock configuration, account for that. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- .../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++ drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+)