From patchwork Sat Mar 13 02:19:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 12136349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB8B9C28E88 for ; Sat, 13 Mar 2021 02:22:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 770A364FA6 for ; Sat, 13 Mar 2021 02:22:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232731AbhCMCVc (ORCPT ); Fri, 12 Mar 2021 21:21:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232955AbhCMCU6 (ORCPT ); Fri, 12 Mar 2021 21:20:58 -0500 Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [IPv6:2001:4b7a:2000:18::165]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34B8EC061761 for ; Fri, 12 Mar 2021 18:20:58 -0800 (PST) Received: from localhost.localdomain (abac242.neoplus.adsl.tpnet.pl [83.6.166.242]) by m-r1.th.seeweb.it (Postfix) with ESMTPA id EFD021F88F; Sat, 13 Mar 2021 03:20:55 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration Date: Sat, 13 Mar 2021 03:19:18 +0100 Message-Id: <20210313021919.435332-9-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210313021919.435332-1-konrad.dybcio@somainline.org> References: <20210313021919.435332-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some devices come with a different SDCC clock configuration, account for that. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++ drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml index f8067fb1bbd6..9db0800a4ee4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -49,6 +49,10 @@ properties: description: Protected clock specifier list as per common clock binding. + qcom,sdcc2-clk-src-40mhz: + description: SDCC2_APPS clock source runs at 40MHz. + type: boolean + required: - compatible - reg diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index a5b9db7678d1..1fbbf5f5dee0 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -1018,6 +1018,19 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { }, }; +static struct freq_tbl ftbl_sdcc2_40mhz_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_GPLL0, 15, 1, 2), + F(25000000, P_GPLL0, 12, 1, 2), + F(40000000, P_GPLL0, 15, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(80000000, P_GPLL0, 7.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(200000000, P_GPLL0, 3, 0, 0), + { } +}; + static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { F(144000, P_XO, 16, 3, 25), F(400000, P_XO, 12, 1, 4), @@ -2793,6 +2806,9 @@ static int gcc_msm8994_probe(struct platform_device *pdev) blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; } + if (of_find_property(dev->of_node, "qcom,sdcc2-clk-src-40mhz", NULL)) + sdcc2_apps_clk_src.freq_tbl = ftbl_sdcc2_40mhz_apps_clk_src; + return qcom_cc_probe(pdev, &gcc_msm8994_desc); }