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Tue, 30 Mar 2021 12:18:21 +0000 From: quanyang.wang@windriver.com To: Michael Turquette , Stephen Boyd , Michal Simek , Laurent Pinchart Cc: Greg Kroah-Hartman , Rajan Vaja , Jolly Shah , Quanyang Wang , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [V2] [PATCH] clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable Date: Tue, 30 Mar 2021 20:17:01 +0800 Message-Id: <20210330121701.3258948-1-quanyang.wang@windriver.com> X-Mailer: git-send-email 2.25.1 X-Originating-IP: [60.247.85.82] X-ClientProxiedBy: HKAPR03CA0034.apcprd03.prod.outlook.com (2603:1096:203:c9::21) To CY4PR11MB0071.namprd11.prod.outlook.com (2603:10b6:910:7a::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from pek-qwang2-d1.wrs.com (60.247.85.82) by HKAPR03CA0034.apcprd03.prod.outlook.com (2603:1096:203:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3999.16 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: lzxe3/LTV86xvk2/0WlrUaYaoHJNfEQrEiyE98+RjdnLM/DJYZboxVugNpKzKLZA6qoQ6wXLVAIm6wmu24s4XaSnzfm8EWlfAhJn6/0zk3E9kgR1Oag72/aKYiGp3HXovlAmLs9su0WkPyChJiNKw53+itTxfaYoMbIqcsjfKSNQZPTbSn23AqL7aZ7kyuMK871Kj+UEZtyGZt1KWq9EdxC/d8XfdZmpVJVeN57Po1P+lm7iI1d0t1wTgDqCz+8d3YlE4eeDwAEGXFZ6lw9SP1Lgj+hY5g6CPeyLftuWqHZCVWSNyowgdVahDgKdOkWN/tUVrhPDh27Xb/sXa5fxfA6NmIW8dw9At25hzRe5x2abHnVISQvP/TmExCir4H4twkdiX/M3ljQRaIXX/iz9AKftX/zaNaOOckdohHVShP5CcZIWnn+M/6WFNg/osP32ARIDUM5sXudA1Ywl11WWc7Cf7UmgJLqQ41JYy+U8r1ebXC1zmOmQtt8FFepImrf3cOGrVLpUs1x5G9QcLiE92U7OmYfDI1VbbmOonsBC5w7xSVbA4mGY/gbshgPr7Jvd6yJKfAi6mn6haYX1Vo6AUK6bYdnquxWlLjYkGAMN3eNxOo72mnHGdCaFuKqofkYRlwzeRXGpl1jvGb0p3MIf1+Mj9ieil2s4ZtFdMJtmhNufUOv6s3e3huJcIRNS6wFhsvsb4wTKCNy+Zmzhzd7HrS71Hl9C9GdgVUV1+c0sMlTFVMQmao/l8C/VEVQq4sy4eIK7XMotJ+spkIgaQH0wqWVqoJiGRl/MEEgSYliVRjAtL9YOwmkVYH7+d3Bn16Tn7yL6TekTZamncQAWyAMsd2g1tUiZeMwKzniRqEtC7lYl6yyRXfRPyXGFA/748nrnbwB7nXx6MPxFp7DNvf1/iTipUt+Dv9dg5mILHJbbhnmyu49ZQElnlAzFemuWccoUktsYtaVpzu2/l87y/mK9pwkA10oDVwftovLdMoXbiLQnz0/GnjeCXqF6xbR+4+CQP/EDUPQUR4Bl69AxZN3dBv/iL92uR+Rx3qLEh9ESGhblSQCccPAbxuTEpciqz0P2ZqrBniQwjFt0HjgxqLPJeQysQGheKwZKXL5RJFaDfRh8amBKUvOeLiRaXxU0Q4TKyOTci1goFmfOi+04igFMKNqOPuErhg2nklDBvleU7Yl34XTG3mKxv9Fp1sbBSE6ywgZLf076VK+jfVhyv6HejYTnIuYFGu+hQRyKmLOTy3bPXp9B0IoHvBSBtVwXE+G0Kd72Xs7UNPJIyBuWuOHuqI3x3zlDL829Hlq2Tyl2lq3YqusY9tdkeSXO9AHIO9t/ X-OriginatorOrg: windriver.com X-MS-Exchange-CrossTenant-Network-Message-Id: 32a4b574-00bd-4335-8abb-08d8f375e854 X-MS-Exchange-CrossTenant-AuthSource: CY4PR11MB0071.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2021 12:18:21.2740 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8ddb2873-a1ad-4a18-ae4e-4644631433be X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZYqtE8FRGFDknmjlWFaMJQ7q6VkRkCLc9JS/Go7Z/7dnh6urpnyFMee6TuHim7kGMIjaqYYxAYJbdQTMs4Ii1XHQ2nc7pmktU4dZUZ9Oy3o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1101MB2341 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Quanyang Wang If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever, we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this pll has been enabled. In ATF implementation, it will only assign the mode to the variable (struct pm_pll *)pll->mode when handling IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force ATF send request to PWU to set the pll mode to PLL's register. There is a scenario that happens in enabling VPLL_INT(clk_id:96): 1) VPLL_INT has been enabled during booting. 2) A driver calls clk_set_rate and according to the rate, the VPLL_INT should be set to FRAC mode. Then zynqmp_pll_set_mode is called to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point ATF just stores the mode to a variable. 3) This driver calls clk_prepare_enable and zynqmp_pll_enable is called to try to enable VPLL_INT pll. Because of 1), the function zynqmp_pll_enable just returns without doing anything after checking that this pll has been enabled. In the scenario above, the pll mode of VPLL_INT will never be set successfully. So adding set_pll_mode to check condition to fix it. Signed-off-by: Quanyang Wang Tested-by: Laurent Pinchart --- V2: - add Tested-by tag, thanks Laurent. - fix typos in commit message and multiline code comments --- drivers/clk/zynqmp/pll.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 92f449ed38e5..fa89ee722a6d 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -14,10 +14,12 @@ * struct zynqmp_pll - PLL clock * @hw: Handle between common and hardware-specific interfaces * @clk_id: PLL clock ID + * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF */ struct zynqmp_pll { struct clk_hw hw; u32 clk_id; + bool set_pll_mode; }; #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw) @@ -81,6 +83,8 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) if (ret) pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); + else + clk->set_pll_mode = true; } /** @@ -240,9 +244,15 @@ static int zynqmp_pll_enable(struct clk_hw *hw) u32 clk_id = clk->clk_id; int ret; - if (zynqmp_pll_is_enabled(hw)) + /* + * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request + * that has been sent to ATF. + */ + if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode)) return 0; + clk->set_pll_mode = false; + ret = zynqmp_pm_clock_enable(clk_id); if (ret) pr_warn_once("%s() clock enable failed for %s, ret = %d\n",