From patchwork Thu Apr 8 18:57:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D35C433ED for ; Thu, 8 Apr 2021 18:57:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D310E61041 for ; Thu, 8 Apr 2021 18:57:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232951AbhDHS6E (ORCPT ); Thu, 8 Apr 2021 14:58:04 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:58863 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS6E (ORCPT ); Thu, 8 Apr 2021 14:58:04 -0400 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrc1MZrz1s0tQ; Thu, 8 Apr 2021 20:57:52 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrc09JHz1sP6L; Thu, 8 Apr 2021 20:57:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id Z338hh1SwnAR; Thu, 8 Apr 2021 20:57:50 +0200 (CEST) X-Auth-Info: fLof6CmnyBaU687AIPkgOjxz+lIqhaGYviSmucAScZM= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:50 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 5/7] ARM: dts: stm32: Add alternate pinmux for ethernet0 pins Date: Thu, 8 Apr 2021 20:57:29 +0200 Message-Id: <20210408185731.135511-6-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add another mux option for ethernet0 pins, this is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and then fed back via PA1 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 060baa8b7e9d..08ab62c9f254 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -305,6 +305,40 @@ pins1 { }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */