| Message ID | 20210519174149.3691335-1-pgwipeout@gmail.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: rockchip: fix rk3568 cpll clk gate bits | expand |
Hi: Michael: Thanks for your patch. Reviewed-by: Elaine Zhang<zhangqing@rock-chips.com> 在 2021/5/20 上午1:41, Peter Geis 写道: > The cpll clk gate bits had an ordering issue. This led to the loss of > the boot sdmmc controller when the gmac was shut down with: > `ip link set eth0 down` > as the cpll_100m was shut off instead of the cpll_62p5. > cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m > misplaced. > > Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568") > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > drivers/clk/rockchip/clk-rk3568.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c > index 946ea2f45bf3..75ca855e720d 100644 > --- a/drivers/clk/rockchip/clk-rk3568.c > +++ b/drivers/clk/rockchip/clk-rk3568.c > @@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { > COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, > RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, > RK3568_CLKGATE_CON(35), 10, GFLAGS), > + COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, > + RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, > + RK3568_CLKGATE_CON(35), 11, GFLAGS), > COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, > RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, > - RK3568_CLKGATE_CON(35), 11, GFLAGS), > + RK3568_CLKGATE_CON(35), 12, GFLAGS), > COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, > RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, > - RK3568_CLKGATE_CON(35), 12, GFLAGS), > + RK3568_CLKGATE_CON(35), 13, GFLAGS), > COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, > RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, > - RK3568_CLKGATE_CON(35), 13, GFLAGS), > - COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, > - RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, > RK3568_CLKGATE_CON(35), 14, GFLAGS), > COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, > RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
On Wed, 19 May 2021 13:41:49 -0400, Peter Geis wrote: > The cpll clk gate bits had an ordering issue. This led to the loss of > the boot sdmmc controller when the gmac was shut down with: > `ip link set eth0 down` > as the cpll_100m was shut off instead of the cpll_62p5. > cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m > misplaced. > > [...] Applied, thanks! [1/1] clk: rockchip: fix rk3568 cpll clk gate bits commit: 2f3877d609e7951ef96d24979eb9d163f1f004f8 Best regards,
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 946ea2f45bf3..75ca855e720d 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 10, GFLAGS), + COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, + RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, + RK3568_CLKGATE_CON(35), 11, GFLAGS), COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 11, GFLAGS), + RK3568_CLKGATE_CON(35), 12, GFLAGS), COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, - RK3568_CLKGATE_CON(35), 12, GFLAGS), + RK3568_CLKGATE_CON(35), 13, GFLAGS), COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, - RK3568_CLKGATE_CON(35), 13, GFLAGS), - COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, - RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, RK3568_CLKGATE_CON(35), 14, GFLAGS), COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
The cpll clk gate bits had an ordering issue. This led to the loss of the boot sdmmc controller when the gmac was shut down with: `ip link set eth0 down` as the cpll_100m was shut off instead of the cpll_62p5. cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m misplaced. Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568") Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- drivers/clk/rockchip/clk-rk3568.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)