diff mbox series

[2/8] clk: imx: pll14xx: Fix masking

Message ID 20220223075601.3652543-3-s.hauer@pengutronix.de (mailing list archive)
State Superseded, archived
Headers show
Series clk: i.MX: PLL14xx: Support dynamic rates | expand

Commit Message

Sascha Hauer Feb. 23, 2022, 7:55 a.m. UTC
The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK
already contains the shifted value, so shifting it again is wrong.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-pll14xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Abel Vesa Feb. 23, 2022, 11:31 a.m. UTC | #1
On 22-02-23 08:55:55, Sascha Hauer wrote:
> The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK
> already contains the shifted value, so shifting it again is wrong.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Do we need some fixes tag, maybe?

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-pll14xx.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> index cae64d750672e..b295d8a049009 100644
> --- a/drivers/clk/imx/clk-pll14xx.c
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -195,7 +195,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
>  	tmp = readl_relaxed(pll->base + DIV_CTL0);
>  
>  	if (!clk_pll14xx_mp_change(rate, tmp)) {
> -		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
> +		tmp &= ~SDIV_MASK;
>  		tmp |= rate->sdiv << SDIV_SHIFT;
>  		writel_relaxed(tmp, pll->base + DIV_CTL0);
>  
> @@ -261,7 +261,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
>  	tmp = readl_relaxed(pll->base + DIV_CTL0);
>  
>  	if (!clk_pll14xx_mp_change(rate, tmp)) {
> -		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
> +		tmp &= ~SDIV_MASK;
>  		tmp |= rate->sdiv << SDIV_SHIFT;
>  		writel_relaxed(tmp, pll->base + DIV_CTL0);
>  
> -- 
> 2.30.2
>
Sascha Hauer Feb. 23, 2022, 11:46 a.m. UTC | #2
On Wed, Feb 23, 2022 at 01:31:09PM +0200, Abel Vesa wrote:
> On 22-02-23 08:55:55, Sascha Hauer wrote:
> > The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK
> > already contains the shifted value, so shifting it again is wrong.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> 
> Do we need some fixes tag, maybe?

Not really. I just realized that SDIV_SHIFT is 0, so this is really only
a cosmetic change.

Sascha

> 
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> 
> > ---
> >  drivers/clk/imx/clk-pll14xx.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> > index cae64d750672e..b295d8a049009 100644
> > --- a/drivers/clk/imx/clk-pll14xx.c
> > +++ b/drivers/clk/imx/clk-pll14xx.c
> > @@ -195,7 +195,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
> >  	tmp = readl_relaxed(pll->base + DIV_CTL0);
> >  
> >  	if (!clk_pll14xx_mp_change(rate, tmp)) {
> > -		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
> > +		tmp &= ~SDIV_MASK;
> >  		tmp |= rate->sdiv << SDIV_SHIFT;
> >  		writel_relaxed(tmp, pll->base + DIV_CTL0);
> >  
> > @@ -261,7 +261,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
> >  	tmp = readl_relaxed(pll->base + DIV_CTL0);
> >  
> >  	if (!clk_pll14xx_mp_change(rate, tmp)) {
> > -		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
> > +		tmp &= ~SDIV_MASK;
> >  		tmp |= rate->sdiv << SDIV_SHIFT;
> >  		writel_relaxed(tmp, pll->base + DIV_CTL0);
> >  
> > -- 
> > 2.30.2
> >
>
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index cae64d750672e..b295d8a049009 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -195,7 +195,7 @@  static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
 	tmp = readl_relaxed(pll->base + DIV_CTL0);
 
 	if (!clk_pll14xx_mp_change(rate, tmp)) {
-		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+		tmp &= ~SDIV_MASK;
 		tmp |= rate->sdiv << SDIV_SHIFT;
 		writel_relaxed(tmp, pll->base + DIV_CTL0);
 
@@ -261,7 +261,7 @@  static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
 	tmp = readl_relaxed(pll->base + DIV_CTL0);
 
 	if (!clk_pll14xx_mp_change(rate, tmp)) {
-		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+		tmp &= ~SDIV_MASK;
 		tmp |= rate->sdiv << SDIV_SHIFT;
 		writel_relaxed(tmp, pll->base + DIV_CTL0);