From patchwork Wed Apr 27 09:48:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12828547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE7D8C433EF for ; Wed, 27 Apr 2022 09:56:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229873AbiD0J7x (ORCPT ); Wed, 27 Apr 2022 05:59:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229697AbiD0J7w (ORCPT ); Wed, 27 Apr 2022 05:59:52 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 04D093FE7E7; Wed, 27 Apr 2022 02:53:12 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.90,292,1643641200"; d="scan'208";a="118179427" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Apr 2022 18:48:57 +0900 Received: from localhost.localdomain (unknown [10.226.93.29]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 53E3D4264DAF; Wed, 27 Apr 2022 18:48:54 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH v2 8/9] clk: renesas: r9a07g044: Add LCDC clock and reset entries Date: Wed, 27 Apr 2022 10:48:22 +0100 Message-Id: <20220427094823.3319-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220427094823.3319-1-biju.das.jz@bp.renesas.com> References: <20220427094823.3319-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add LCDC clock and reset entries to CPG driver. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- V1->V2: * No change RFC->V1: * Added Rb tag from Geert --- drivers/clk/renesas/r9a07g044-cpg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 66608696d2e2..b5ddc5058670 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -194,7 +194,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[62]; + struct rzg2l_mod_clk common[65]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -254,6 +254,12 @@ static const struct { 0x558, 1), DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 0x558, 2), + DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, + 0x56c, 0), + DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, + 0x56c, 0), + DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3, + 0x56c, 1), DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 0x570, 0), DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, @@ -349,6 +355,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), + DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0), DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),