From patchwork Sat Apr 30 11:41:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12833136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4544BC433FE for ; Sat, 30 Apr 2022 11:42:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237917AbiD3Lpj (ORCPT ); Sat, 30 Apr 2022 07:45:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237218AbiD3Lpi (ORCPT ); Sat, 30 Apr 2022 07:45:38 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 37CEB5DBF3; Sat, 30 Apr 2022 04:42:17 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,187,1647270000"; d="scan'208";a="118460243" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Apr 2022 20:42:16 +0900 Received: from localhost.localdomain (unknown [10.226.92.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7422C42325D8; Sat, 30 Apr 2022 20:42:13 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH v3 4/9] clk: renesas: r9a07g044: Add M1 clock support Date: Sat, 30 Apr 2022 12:41:51 +0100 Message-Id: <20220430114156.6260-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220430114156.6260-1-biju.das.jz@bp.renesas.com> References: <20220430114156.6260-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add support for M1 clock which is sourced from FOUTPOSTDIV. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- V2->V3: * No change V1->V2: * No change RFC->V1: * Added Rb tag from Geert --- drivers/clk/renesas/r9a07g044-cpg.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index bdfabb992a20..0c9fa1f705af 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -40,6 +40,8 @@ enum clk_ids { CLK_DIV_PLL3_C, CLK_PLL4, CLK_PLL5, + CLK_PLL5_FOUTPOSTDIV, + CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUT3, CLK_PLL5_250, CLK_PLL6, @@ -52,6 +54,7 @@ enum clk_ids { CLK_SD0_DIV4, CLK_SD1_DIV4, CLK_SEL_GPU2, + CLK_SEL_PLL5_4, /* Module Clocks */ MOD_CLK_BASE, @@ -77,12 +80,13 @@ static const struct clk_div_table dtable_1_32[] = { /* Mux clock tables */ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; +static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; static const struct { - struct cpg_core_clk common[44]; + struct cpg_core_clk common[48]; #ifdef CONFIG_CLK_R9A07G054 struct cpg_core_clk drp[0]; #endif @@ -127,6 +131,10 @@ static const struct { DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), + DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), + DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), + DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, + sel_pll5_4, ARRAY_SIZE(sel_pll5_4)), /* Core output clk */ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, @@ -154,6 +162,7 @@ static const struct { DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), }, #ifdef CONFIG_CLK_R9A07G054 .drp = {