| Message ID | 20220501083450.26541-5-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add RZ/G2UL CLK and Reset entries for RSPI,TSU,ADC and SPI Multi IO Bus Controller | expand |
On Sun, May 1, 2022 at 10:35 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add clock and reset entries for ADC block in CPG driver. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.19. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 70b1226cf294..7ef2c43ea891 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -243,6 +243,10 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x594, 0), DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 0x598, 0), + DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, + 0x5a8, 0), + DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, + 0x5a8, 1), DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 0x5ac, 0), }; @@ -290,6 +294,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), + DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), };
Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a07g043-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+)