From patchwork Sun May 1 08:34:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12833558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E82D9C433F5 for ; Sun, 1 May 2022 08:35:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245606AbiEAIif (ORCPT ); Sun, 1 May 2022 04:38:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245496AbiEAIif (ORCPT ); Sun, 1 May 2022 04:38:35 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9E1E6B6F; Sun, 1 May 2022 01:35:09 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,189,1647270000"; d="scan'208";a="119713766" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 01 May 2022 17:35:09 +0900 Received: from localhost.localdomain (unknown [10.226.92.14]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8ACEB4006CCF; Sun, 1 May 2022 17:35:06 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 4/4] clk: renesas: r9a07g043: Add clock and reset entries for ADC Date: Sun, 1 May 2022 09:34:50 +0100 Message-Id: <20220501083450.26541-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220501083450.26541-1-biju.das.jz@bp.renesas.com> References: <20220501083450.26541-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 70b1226cf294..7ef2c43ea891 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -243,6 +243,10 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x594, 0), DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 0x598, 0), + DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, + 0x5a8, 0), + DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, + 0x5a8, 1), DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 0x5ac, 0), }; @@ -290,6 +294,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), + DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), };