@@ -2,6 +2,7 @@
// Copyright 2021 Jonathan Neuschäfer
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/nuvoton,wpcm450-clk.h>
/ {
compatible = "nuvoton,wpcm450";
@@ -32,13 +33,6 @@ cpu@0 {
};
};
- clk24m: clock-24mhz {
- /* 24 MHz dummy clock */
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- #clock-cells = <0>;
- };
-
refclk: clock-48mhz {
/* 48 MHz reference oscillator */
compatible = "fixed-clock";
@@ -73,7 +67,7 @@ serial0: serial@b8000000 {
reg = <0xb8000000 0x20>;
reg-shift = <2>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk24m>;
+ clocks = <&clk WPCM450_CLK_UART0>;
pinctrl-names = "default";
pinctrl-0 = <&bsp_pins>;
status = "disabled";
@@ -84,7 +78,7 @@ serial1: serial@b8000100 {
reg = <0xb8000100 0x20>;
reg-shift = <2>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk24m>;
+ clocks = <&clk WPCM450_CLK_UART1>;
status = "disabled";
};
@@ -92,14 +86,18 @@ timer0: timer@b8001000 {
compatible = "nuvoton,wpcm450-timer";
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb8001000 0x1c>;
- clocks = <&clk24m>;
+ clocks = <&clk WPCM450_CLK_TIMER0>,
+ <&clk WPCM450_CLK_TIMER1>,
+ <&clk WPCM450_CLK_TIMER2>,
+ <&clk WPCM450_CLK_TIMER3>,
+ <&clk WPCM450_CLK_TIMER4>;
};
watchdog0: watchdog@b800101c {
compatible = "nuvoton,wpcm450-wdt";
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb800101c 0x4>;
- clocks = <&clk24m>;
+ clocks = <&clk WPCM450_CLK_WDT>;
};
aic: interrupt-controller@b8002000 {
This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> --- v2, v3: - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -- 2.35.1