| Message ID | 20220518172808.1691450-3-ralph.siemsen@linaro.org (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel | expand |
Hi Ralph, Thanks for your patch! On 18 May 2022 18:27 Ralph Siemsen wrote: > As the D_UGATE macro no longer uses _gi, drop it from all declarations. > > Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> > --- > drivers/clk/renesas/r9a06g032-clocks.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/clk/renesas/r9a06g032-clocks.c > b/drivers/clk/renesas/r9a06g032-clocks.c > index 9dbcf9620fa0..fe56560c54df 100644 > --- a/drivers/clk/renesas/r9a06g032-clocks.c > +++ b/drivers/clk/renesas/r9a06g032-clocks.c > @@ -79,7 +79,7 @@ struct r9a06g032_clkdesc { > .source = 1 + R9A06G032_##_src, .name = _n, \ > .reg = _reg, .div_min = _min, .div_max = _max, \ > .div_table = { __VA_ARGS__ } } > -#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \ > +#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \ > { .type = K_DUALGATE, .index = R9A06G032_##_idx, \ > .source = 1 + R9A06G032_##_src, .name = _n, \ > .dual = { .group = _g, \ > @@ -297,14 +297,14 @@ static const struct r9a06g032_clkdesc > r9a06g032_clocks[] = { > .dual.sel = ((0xec / 4) << 5) | 24, > .dual.group = 1, > }, > - D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, > 0x1b4, 0x1b5), > - D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, > 0x1b8, 0x1b9), > - D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, > 0x1bc, 0x1bd), > - D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, > 0x761, 0x762, 0x763), > - D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, > 0x765, 0x766, 0x767), > - D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, > 0x769, 0x76a, 0x76b), > - D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, > 0x76d, 0x76e, 0x76f), > - D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, > 0x771, 0x772, 0x773), > + D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, > 0x1b4, 0x1b5), > + D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, > 0x1b8, 0x1b9), > + D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, > 0x1bc, 0x1bd), > + D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, > 0x762, 0x763), > + D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, > 0x766, 0x767), > + D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, > 0x76a, 0x76b), > + D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, > 0x76e, 0x76f), > + D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, > 0x772, 0x773), > }; > > struct r9a06g032_priv { > -- > 2.25.1 Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Thanks Phil
On Wed, May 18, 2022 at 7:29 PM Ralph Siemsen <ralph.siemsen@linaro.org> wrote: > As the D_UGATE macro no longer uses _gi, drop it from all declarations. > > Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.20, folded into [PATCH 2/3]. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 9dbcf9620fa0..fe56560c54df 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -79,7 +79,7 @@ struct r9a06g032_clkdesc { .source = 1 + R9A06G032_##_src, .name = _n, \ .reg = _reg, .div_min = _min, .div_max = _max, \ .div_table = { __VA_ARGS__ } } -#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \ +#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \ { .type = K_DUALGATE, .index = R9A06G032_##_idx, \ .source = 1 + R9A06G032_##_src, .name = _n, \ .dual = { .group = _g, \ @@ -297,14 +297,14 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .dual.sel = ((0xec / 4) << 5) | 24, .dual.group = 1, }, - D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), - D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9), - D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd), - D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763), - D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767), - D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b), - D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f), - D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773), + D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), + D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9), + D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd), + D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763), + D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767), + D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b), + D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f), + D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773), }; struct r9a06g032_priv {
As the D_UGATE macro no longer uses _gi, drop it from all declarations. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> --- drivers/clk/renesas/r9a06g032-clocks.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)