| Message ID | 20220915092927.4158755-1-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | [GIT,PULL] Microchip clock updates for 6.1 | expand |
Quoting Claudiu Beznea (2022-09-15 02:29:27) > Hi, Stephen, Michael, > > On Microchip we decided to send a single clock pull request for both > AT91 and Polarfire architectures. Let us know if you would prefer otherwise. > > Please note that this PR is based on Microchip clock fixes PR. > > Thank you, > Claudiu Beznea > > The following changes since commit 05d27090b6dc88bce71a608d1271536e582b73d1: > > clk: microchip: mpfs: make the rtc's ahb clock critical (2022-09-14 10:45:52 +0300) > > are available in the Git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git tags/clk-microchip-6.1 > > for you to fetch changes up to 935edf0c145596c26e7c6825918acde27ff94ff6: > > clk: at91: sama5d2: Add Generic Clocks for UART/USART (2022-09-15 11:01:37 +0300) > > ---------------------------------------------------------------- Thanks. Pulled into clk-next
Hi, Stephen, Michael, On Microchip we decided to send a single clock pull request for both AT91 and Polarfire architectures. Let us know if you would prefer otherwise. Please note that this PR is based on Microchip clock fixes PR. Thank you, Claudiu Beznea The following changes since commit 05d27090b6dc88bce71a608d1271536e582b73d1: clk: microchip: mpfs: make the rtc's ahb clock critical (2022-09-14 10:45:52 +0300) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git tags/clk-microchip-6.1 for you to fetch changes up to 935edf0c145596c26e7c6825918acde27ff94ff6: clk: at91: sama5d2: Add Generic Clocks for UART/USART (2022-09-15 11:01:37 +0300) ---------------------------------------------------------------- Microchip clock update for 6.1 Microchip AT91: - add generic clocks for U(S)ART available on SAMA5D2 SoCs Microchip Polarfire: - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry ---------------------------------------------------------------- Conor Dooley (15): dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: add reset controller reset: add polarfire soc reset support MAINTAINERS: add polarfire soc reset controller clk: microchip: mpfs: add MSS pll's set & round rate clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: update module authorship & licencing dt-bindings: clk: rename mpfs-clkcfg binding dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: add PolarFire SoC fabric clock ids clk: microchip: add PolarFire SoC fabric clock support Sergiu Moga (1): clk: at91: sama5d2: Add Generic Clocks for UART/USART .../bindings/clock/microchip,mpfs-ccc.yaml | 80 +++++ ...rochip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 19 +- MAINTAINERS | 1 + drivers/clk/at91/sama5d2.c | 10 + drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-mpfs-ccc.c | 290 ++++++++++++++++ drivers/clk/microchip/clk-mpfs.c | 375 ++++++++++----------- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 157 +++++++++ include/dt-bindings/clock/microchip,mpfs-clock.h | 23 ++ include/soc/microchip/mpfs.h | 8 + 13 files changed, 780 insertions(+), 194 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (73%) create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c create mode 100644 drivers/reset/reset-mpfs.c