| Message ID | 20221010155546.73884-1-konrad.dybcio@somainline.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: qcom: dispcc-sm6350: Add CLK_OPS_PARENT_ENABLE to pixel&byte src | expand |
Quoting Konrad Dybcio (2022-10-10 08:55:46) > Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to > ensure set_rate can succeed. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- Any Fixes tag?
On 2022-10-11 03:02, Stephen Boyd wrote: > Quoting Konrad Dybcio (2022-10-10 08:55:46) >> Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to >> ensure set_rate can succeed. >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> --- > > Any Fixes tag? Sorry, I keep forgetting.. Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") Konrad
On Mon, 10 Oct 2022 17:55:46 +0200, Konrad Dybcio wrote: > Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to > ensure set_rate can succeed. > > Applied, thanks! [1/1] clk: qcom: dispcc-sm6350: Add CLK_OPS_PARENT_ENABLE to pixel&byte src commit: 92039e8c080c63748f8e133e7cfad33a75daefb6 Best regards,
diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c index 0c3c2e26ede9..ea6f54ed846e 100644 --- a/drivers/clk/qcom/dispcc-sm6350.c +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE, .ops = &clk_pixel_ops, }, }; @@ -385,7 +385,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE, .ops = &clk_branch2_ops, }, },
Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to ensure set_rate can succeed. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- drivers/clk/qcom/dispcc-sm6350.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)