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Tue, 22 Nov 2022 06:13:24 -0600 From: Shubhrajyoti Datta To: CC: , , , , , , Subject: [PATCH v3 1/2] dt-bindings: clk: Add binding for versal clocking wizard Date: Tue, 22 Nov 2022 17:42:54 +0530 Message-ID: <20221122121255.6823-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221122121255.6823-1-shubhrajyoti.datta@amd.com> References: <20221122121255.6823-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT046:EE_|SJ1PR12MB6121:EE_ X-MS-Office365-Filtering-Correlation-Id: f7807abb-8d2f-4a24-12c0-08dacc830cc9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AsGff80mtSVy+w3Xz90Eh9sGbDB5J5deBA7qwSBshyjkISuYLceU4kFlwjx1Yd1MpuH/7KeSyFzLJ5AzNPAOCI11t7i8gpqRehQUJsluCcUySWfvKcdhKILbWE3WRFdUtz9sfgHPcsRCdMqzgGEIh+4NoSlZtB/zS5027V1Q5f3rwT2F6lfWuXpgbaoaC7u3wj4om3fFf0A5I02RDdkMhRJ1vcVa1WGwqDE/hUp9uxY+FNCK/IdPr5qWahiYvDsUEPxktREzFHMXl/+0H5WbjqHWrODb6GRm0Ja+x4JeDLfWxTtBvQrmKtmHDH14olVM7blKhI8GG2oPMjq6HzXmn7zJLYJtgh9HR8OaWmfvk4D3qm1s0BzFEw6gadIwZM32iShLU9H4H0EC0r4e5g0GYgSo2YTUUhVzwOy/ab4vM4tT3DX4R8Ov49D/DN4Qhb00UE62ln4mZyctf2qeN/Rz7xfzo66YBKpbOl/U5e60pRgZKh2CEsHUUYaPeIBKaFZGcqNdolEsy+Xz3mY+E5VcBqMDK+P09bUGAGMdAK+3AKjKsJUirmvrZ6FPrsJNwK391qwfj3wbNBujVKXnHFP9HDpXOqueUM3zSf8bsWB+3LZui803HTZybH4erd/eAnVw1FjZm9XtB7JY68YJ4Ey/6dwr/jlz6IBU+kKegXYjupsVGe1pFcWgVJVgdCl0rrt5cifpA9NK1m7VnYBzBGMetm60u7puglujApoYNMlDvdKiuHbehJLyWeZ8ApxJqoYfBdiU2u65QRiRORaOwq1L9vN7WM7bIt82rGPjLQo0NWg3byHtsgzfUJOcU8JnbICa X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(346002)(39860400002)(136003)(451199015)(40470700004)(46966006)(36840700001)(26005)(2906002)(356005)(81166007)(82740400003)(6666004)(86362001)(36756003)(83380400001)(478600001)(40460700003)(36860700001)(2616005)(1076003)(336012)(47076005)(82310400005)(426003)(186003)(8936002)(44832011)(41300700001)(966005)(40480700001)(4326008)(8676002)(6916009)(70586007)(5660300002)(70206006)(316002)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2022 12:14:05.2851 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7807abb-8d2f-4a24-12c0-08dacc830cc9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6121 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Clocking Wizard for Versal adaptive compute acceleration platforms generates multiple configurable number of clock outputs. Add device tree binding for Versal clocking wizard support. Signed-off-by: Shubhrajyoti Datta --- Changes in v3: rename the clocks to clk_in1 and s_axi_clk dt Changes in v2: rename the clocks clk_in1 to in1 and s_axi_clk to s_axi in dt .../clock/xlnx,versal-clk-wizard.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml new file mode 100644 index 000000000000..cd3c329ddd29 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,versal-clk-wizard.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal clocking wizard + +maintainers: + - Shubhrajyoti Datta + +description: + The clocking wizard is a soft ip clocking block of Xilinx Versal. The IP + uses the input clock frequencies and generates the requested + clock output. + +properties: + compatible: + const: xlnx,versal-clk-wizard + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + description: External input clocks to the given clock controller. + items: + - description: functional clock input + - description: axi clock or the interface clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + xlnx,nr-outputs: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + description: + Number of outputs. + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - xlnx,nr-outputs + +additionalProperties: false + +examples: + - | + clock-generator@40040000 { + compatible = "xlnx,versal-clk-wizard"; + reg = <0x40040000 0x1000>; + #clock-cells = <1>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "clk_in1", "s_axi_aclk"; + xlnx,nr-outputs = <6>; + }; +...