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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id r126-20020a1c2b84000000b003d35c845cbbsm19927757wmr.21.2023.01.10.10.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 10:33:12 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 6/6] ARM: dts: qcom: fix various wrong definition for kpss-acc-v2 Date: Tue, 10 Jan 2023 19:32:59 +0100 Message-Id: <20230110183259.19142-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230110183259.19142-1-ansuelsmth@gmail.com> References: <20230110183259.19142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Fix dtbs_check warning now that we have a correct kpss-acc-v2 yaml schema. Change acc node naming to power-controller and add missing binding #power-domain-cells for each kpss-acc-v2 power-controller to reflect Documentation schema. Signed-off-by: Christian Marangi --- arch/arm/boot/dts/qcom-apq8084.dtsi | 12 ++++++++---- arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++---- arch/arm/boot/dts/qcom-msm8974.dtsi | 12 ++++++++---- 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 4b0d2b4f4b6a..51c5867eb950 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -353,28 +353,32 @@ saw_l2: power-controller@f9012000 { regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-controller@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc1: clock-controller@f9098000 { + acc1: power-controller@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc2: clock-controller@f90a8000 { + acc2: power-controller@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc3: clock-controller@f90b8000 { + acc3: power-controller@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; restart@fc4ab000 { diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index acb08dcf9442..ee464aedece9 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -325,24 +325,28 @@ crypto: crypto@8e3a000 { status = "disabled"; }; - acc0: clock-controller@b088000 { + acc0: power-controller@b088000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; - acc1: clock-controller@b098000 { + acc1: power-controller@b098000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; - acc2: clock-controller@b0a8000 { + acc2: power-controller@b0a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; - acc3: clock-controller@b0b8000 { + acc3: power-controller@b0b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; saw0: regulator@b089000 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 4b485f5612c4..59613aa52e25 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -416,24 +416,28 @@ saw_l2: power-controller@f9012000 { regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-controller@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc1: clock-controller@f9098000 { + acc1: power-controller@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc2: clock-controller@f90a8000 { + acc2: power-controller@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc3: clock-controller@f90b8000 { + acc3: power-controller@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; sdhc_1: mmc@f9824900 {