@@ -32,12 +32,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
- audio_mclock: audio_mclock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -55,7 +49,6 @@ cpu_dai: simple-audio-card,cpu {
};
codec_dai: simple-audio-card,codec {
- clocks = <&audio_mclock>;
sound-dai = <&wm8978>;
};
};
@@ -16,12 +16,22 @@ aliases {
serial1 = &scif2;
i2c3 = &i2c3;
};
+
+ x1_x2: xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
};
&cpu_dai {
sound-dai = <&ssi0>;
};
+&codec_dai {
+ clocks = <&versa3 3>;
+};
+
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
@@ -29,6 +39,31 @@ &i2c3 {
status = "okay";
+ versa3: versa3@68 {
+ compatible = "renesas,5p35023";
+ reg = <0x68>;
+ #clock-cells = <1>;
+ clocks = <&x1_x2>;
+ clock-names = "x1";
+ renesas,settings = [
+ 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
+ 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
+ 80 b0 45 c4 95
+ ];
+ assigned-clocks = <&versa3 0>,
+ <&versa3 1>,
+ <&versa3 2>,
+ <&versa3 3>,
+ <&versa3 4>,
+ <&versa3 5>;
+ assigned-clock-rates = <12288000>, <25000000>,
+ <12000000>, <11289600>,
+ <11289600>, <24000000>;
+ renesas,clock-divider-read-only = <1>, <1>, <1>, <1>, <1>;
+ renesas,clock-flags = <2176>, <2176>, <2176>, <2052>,
+ <2176>, <2048>;
+ };
+
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
Currently audio mclk uses a fixed clk 11.2896MHz(multiple of 44.1KHz). Replace this fixed clk to programmable versa3 clk that can provide 2 rates 11.2896MHz and 12.2880(multiple of 48KHz) based on audio sampling rate for the playback/record. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/rz-smarc-common.dtsi | 7 ---- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 35 +++++++++++++++++++ 2 files changed, 35 insertions(+), 7 deletions(-)