| Message ID | 20230508114236.8444-1-marex@denx.de (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v8,1/2] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX | expand |
On Mon, May 08, 2023 at 01:42:35PM +0200, Marek Vasut wrote: > Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is > needed to get audio operational on i.MX8MP . > > Acked-by: Peng Fan <peng.fan@nxp.com> > Reviewed-by: Fabio Estevam <festevam@gmail.com> > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> > Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Tested-by: Richard Leitner <richard.leitner@skidata.com> > Signed-off-by: Marek Vasut <marex@denx.de> Applied both, thanks!
On Mon, May 8, 2023 at 6:42 AM Marek Vasut <marex@denx.de> wrote: > > Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is > needed to get audio operational on i.MX8MP . > > Acked-by: Peng Fan <peng.fan@nxp.com> > Reviewed-by: Fabio Estevam <festevam@gmail.com> > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> > Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Tested-by: Richard Leitner <richard.leitner@skidata.com> > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Abel Vesa <abelvesa@kernel.org> > Cc: Alexander Stein <alexander.stein@ew.tq-group.com> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Jacky Bai <ping.bai@nxp.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Cc: Luca Ceresoli <luca.ceresoli@bootlin.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Marco Felsch <m.felsch@pengutronix.de> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Richard Cochran <richardcochran@gmail.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-clk@vger.kernel.org > --- > V2: - Add AUDIO_AXI clock to audio gpc > - Use IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT for SDMA2 IPG clock > V3: Rename audio_ahb to plain ahb > V4: - Add RB/TB from Luca > - Rebase on next 20230223 > V5: - Add TB from Adam and Alexander > - Replace blk-ctrl@ with clock-controller@ > - Specify sound-dai-cells in sai nodes > V6: - Add RB from Fabio > - Drop power-domain-names from audiomix block/clock controller > - Move reg below compatible property > - Move sound-dai-cells below reg property > - Sort DT properties: compatible, regs, #cells, properties, status > V7: - Move #clock-cells below reg property > - Add AB from Peng > - Add RB from Marco, sort the tags > V8: Add TB from Richard > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 158 ++++++++++++++++++++++ > 1 file changed, 158 insertions(+) > <snip> Marek, I have a question about the clocking for eASRC and PDM. > + > + audio_blk_ctrl: clock-controller@30e20000 { > + compatible = "fsl,imx8mp-audio-blk-ctrl"; > + reg = <0x30e20000 0x10000>; > + #clock-cells = <1>; > + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, > + <&clk IMX8MP_CLK_SAI1>, > + <&clk IMX8MP_CLK_SAI2>, > + <&clk IMX8MP_CLK_SAI3>, > + <&clk IMX8MP_CLK_SAI5>, > + <&clk IMX8MP_CLK_SAI6>, > + <&clk IMX8MP_CLK_SAI7>; > + clock-names = "ahb", > + "sai1", "sai2", "sai3", > + "sai5", "sai6", "sai7"; > + power-domains = <&pgc_audio>; > + }; > + }; > + I am trying to plumb in the micfil driver with a PDM microphone on a Plus. I have SAI3 and SAI5 audio working, but if I try to use the micfil, the PDM clock doesn't get turned on, and the micfil doesn't appear to see anything coming in. I was curious why the audio_blk_ctrl has clock entries for IMX8MP_CLK_SAIx, but there isn't one for the PDM nor the ASRC clocks. I added the MICFIL noted to the 8mp in a previous patch [1], and I am trying to customize the MICFIL node as follows: &micfil { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pdm>; assigned-clocks = <&clk IMX8MP_CLK_PDM>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <196608000>; status = "okay"; }; I also noticed in the down-stream kernel, the pdm_ipg_clk and pdm_root_clk are shared gates with separate parents. The PDM tree of the down-stream kernel looks like this: audio_pll1_ref_sel 0 0 0 24000000 0 0 50000 Y audio_pll1 0 0 0 393216000 0 0 50000 Y audio_pll1_bypass 0 0 0 393216000 0 0 50000 Y audio_pll1_out 0 0 0 393216000 0 0 50000 N pdm 0 0 0 196608000 0 0 50000 N pdm_root 0 0 0 196608000 0 0 50000 N pdm_sel 0 0 0 196608000 0 0 50000 Y pdm_root_clk 0 0 0 196608000 0 0 50000 N The PDM tree of the mainline looks like this: audio_pll1_ref_sel 0 0 0 24000000 0 0 50000 Y audio_pll1 0 0 0 393216000 0 0 50000 Y audio_pll1_bypass 0 0 0 393216000 0 0 50000 Y audio_pll1_out 0 0 0 393216000 0 0 50000 N pdm 0 0 0 196608000 0 0 50000 N pdm_root 0 0 0 196608000 0 0 50000 N pdm_sel 0 0 0 196608000 0 0 50000 Y It seems like the "pdm_root_clk" generated by the shared audo-blk down-sream driver is missing from the mainline. I looked up the clock I referenced when I attempted to enable the miffil, but 'IMX8MP_CLK_AUDIOMIX_PDM_ROOT doesn't appear to be configured in either clk-imx8mp.c or clk-imx8mp-audiomix.c. Maybe it's obscured by the macros, but it seems like the pdm_sel should somehow have an additional variable for the shared clock and an additional clock like pdm_root_clk assigned with it. I have similar configurations for Mini and Nano, and both of them are able to record audio, so I think there might be a clock issue somewhere related to the audiomix driver, and not a misconfiguration of the sound-card or the micfil itself. thanks for any suggestions, adam [1] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230827023155.467807-3-aford173@gmail.com/
On 8/30/23 04:44, Adam Ford wrote: Hi, > I have a question about the clocking for eASRC and PDM. > >> + >> + audio_blk_ctrl: clock-controller@30e20000 { >> + compatible = "fsl,imx8mp-audio-blk-ctrl"; >> + reg = <0x30e20000 0x10000>; >> + #clock-cells = <1>; >> + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, >> + <&clk IMX8MP_CLK_SAI1>, >> + <&clk IMX8MP_CLK_SAI2>, >> + <&clk IMX8MP_CLK_SAI3>, >> + <&clk IMX8MP_CLK_SAI5>, >> + <&clk IMX8MP_CLK_SAI6>, >> + <&clk IMX8MP_CLK_SAI7>; >> + clock-names = "ahb", >> + "sai1", "sai2", "sai3", >> + "sai5", "sai6", "sai7"; >> + power-domains = <&pgc_audio>; >> + }; >> + }; >> + > > I am trying to plumb in the micfil driver with a PDM microphone on a > Plus. I have SAI3 and SAI5 audio working, but if I try to use the > micfil, the PDM clock doesn't get turned on, and the micfil doesn't > appear to see anything coming in. I was curious why the > audio_blk_ctrl has clock entries for IMX8MP_CLK_SAIx, but there isn't > one for the PDM nor the ASRC clocks. I only ever needed SAI, so that was what was tested on the EVK . > I added the MICFIL noted to the > 8mp in a previous patch [1], and I am trying to customize the MICFIL > node as follows: > > &micfil { > #sound-dai-cells = <0>; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_pdm>; > assigned-clocks = <&clk IMX8MP_CLK_PDM>; > assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; > assigned-clock-rates = <196608000>; > status = "okay"; > }; > > I also noticed in the down-stream kernel, the pdm_ipg_clk and > pdm_root_clk are shared gates with separate parents. > > The PDM tree of the down-stream kernel looks like this: > audio_pll1_ref_sel 0 0 0 24000000 > 0 0 50000 Y > audio_pll1 0 0 0 393216000 > 0 0 50000 Y > audio_pll1_bypass 0 0 0 393216000 > 0 0 50000 Y > audio_pll1_out 0 0 0 393216000 > 0 0 50000 N > pdm 0 0 0 196608000 > 0 0 50000 N > pdm_root 0 0 0 196608000 > 0 0 50000 N > pdm_sel 0 0 0 196608000 > 0 0 50000 Y > pdm_root_clk 0 0 0 > 196608000 0 0 50000 N > > The PDM tree of the mainline looks like this: > > audio_pll1_ref_sel 0 0 0 24000000 > 0 0 50000 Y > audio_pll1 0 0 0 393216000 > 0 0 50000 Y > audio_pll1_bypass 0 0 0 393216000 > 0 0 50000 Y > audio_pll1_out 0 0 0 393216000 > 0 0 50000 N > pdm 0 0 0 196608000 > 0 0 50000 N > pdm_root 0 0 0 196608000 > 0 0 50000 N > pdm_sel 0 0 0 196608000 > 0 0 50000 Y > > It seems like the "pdm_root_clk" generated by the shared audo-blk > down-sream driver is missing from the mainline. I looked up the clock > I referenced when I attempted to enable the miffil, but > 'IMX8MP_CLK_AUDIOMIX_PDM_ROOT doesn't appear to be configured in > either clk-imx8mp.c or clk-imx8mp-audiomix.c. Maybe it's obscured by > the macros, but it seems like the pdm_sel should somehow have an > additional variable for the shared clock and an additional clock like > pdm_root_clk assigned with it. > > I have similar configurations for Mini and Nano, and both of them are > able to record audio, so I think there might be a clock issue > somewhere related to the audiomix driver, and not a misconfiguration > of the sound-card or the micfil itself. Shouldn't the micfil be somehow a consumer of the pdm_sel clock , and enable those clock in the driver ?
On Wed, Aug 30, 2023 at 2:10 PM Marek Vasut <marex@denx.de> wrote: > > On 8/30/23 04:44, Adam Ford wrote: > > Hi, > > > I have a question about the clocking for eASRC and PDM. > > > >> + > >> + audio_blk_ctrl: clock-controller@30e20000 { > >> + compatible = "fsl,imx8mp-audio-blk-ctrl"; > >> + reg = <0x30e20000 0x10000>; > >> + #clock-cells = <1>; > >> + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, > >> + <&clk IMX8MP_CLK_SAI1>, > >> + <&clk IMX8MP_CLK_SAI2>, > >> + <&clk IMX8MP_CLK_SAI3>, > >> + <&clk IMX8MP_CLK_SAI5>, > >> + <&clk IMX8MP_CLK_SAI6>, > >> + <&clk IMX8MP_CLK_SAI7>; > >> + clock-names = "ahb", > >> + "sai1", "sai2", "sai3", > >> + "sai5", "sai6", "sai7"; > >> + power-domains = <&pgc_audio>; > >> + }; > >> + }; > >> + > > > > I am trying to plumb in the micfil driver with a PDM microphone on a > > Plus. I have SAI3 and SAI5 audio working, but if I try to use the > > micfil, the PDM clock doesn't get turned on, and the micfil doesn't > > appear to see anything coming in. I was curious why the > > audio_blk_ctrl has clock entries for IMX8MP_CLK_SAIx, but there isn't > > one for the PDM nor the ASRC clocks. > > I only ever needed SAI, so that was what was tested on the EVK . That makes sense. > > > I added the MICFIL noted to the > > 8mp in a previous patch [1], and I am trying to customize the MICFIL > > node as follows: > > > > &micfil { > > #sound-dai-cells = <0>; > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_pdm>; > > assigned-clocks = <&clk IMX8MP_CLK_PDM>; > > assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; > > assigned-clock-rates = <196608000>; > > status = "okay"; > > }; > > > > I also noticed in the down-stream kernel, the pdm_ipg_clk and > > pdm_root_clk are shared gates with separate parents. > > > > The PDM tree of the down-stream kernel looks like this: > > audio_pll1_ref_sel 0 0 0 24000000 > > 0 0 50000 Y > > audio_pll1 0 0 0 393216000 > > 0 0 50000 Y > > audio_pll1_bypass 0 0 0 393216000 > > 0 0 50000 Y > > audio_pll1_out 0 0 0 393216000 > > 0 0 50000 N > > pdm 0 0 0 196608000 > > 0 0 50000 N > > pdm_root 0 0 0 196608000 > > 0 0 50000 N > > pdm_sel 0 0 0 196608000 > > 0 0 50000 Y > > pdm_root_clk 0 0 0 > > 196608000 0 0 50000 N > > > > The PDM tree of the mainline looks like this: > > > > audio_pll1_ref_sel 0 0 0 24000000 > > 0 0 50000 Y > > audio_pll1 0 0 0 393216000 > > 0 0 50000 Y > > audio_pll1_bypass 0 0 0 393216000 > > 0 0 50000 Y > > audio_pll1_out 0 0 0 393216000 > > 0 0 50000 N > > pdm 0 0 0 196608000 > > 0 0 50000 N > > pdm_root 0 0 0 196608000 > > 0 0 50000 N > > pdm_sel 0 0 0 196608000 > > 0 0 50000 Y > > > > It seems like the "pdm_root_clk" generated by the shared audo-blk > > down-sream driver is missing from the mainline. I looked up the clock > > I referenced when I attempted to enable the miffil, but > > 'IMX8MP_CLK_AUDIOMIX_PDM_ROOT doesn't appear to be configured in > > either clk-imx8mp.c or clk-imx8mp-audiomix.c. Maybe it's obscured by > > the macros, but it seems like the pdm_sel should somehow have an > > additional variable for the shared clock and an additional clock like > > pdm_root_clk assigned with it. > > > > I have similar configurations for Mini and Nano, and both of them are > > able to record audio, so I think there might be a clock issue > > somewhere related to the audiomix driver, and not a misconfiguration > > of the sound-card or the micfil itself. > > Shouldn't the micfil be somehow a consumer of the pdm_sel clock , and > enable those clock in the driver ? Micfil references IMX8MP_CLK_AUDIOMIX_PDM_IPG, and IMX8MP_CLK_AUDIOMIX_PDM_ROOT. I am not convinced the IMX8MP_CLK_AUDIOMIX_PDM_ROOT exists beyond a #define in an include directory. I tried making it use pdm_sel, but it threw an error. I am not near my system, so I'm sorry I don't have more details. In the downstream kernel IMX8MP_CLK_AUDIOMIX_PDM_ROOT was a child of pdm_sel, but I am not certain as to what the difference between them was since they appeared to be shared. adam
On 8/30/23 21:59, Adam Ford wrote: > On Wed, Aug 30, 2023 at 2:10 PM Marek Vasut <marex@denx.de> wrote: >> >> On 8/30/23 04:44, Adam Ford wrote: >> >> Hi, >> >>> I have a question about the clocking for eASRC and PDM. >>> >>>> + >>>> + audio_blk_ctrl: clock-controller@30e20000 { >>>> + compatible = "fsl,imx8mp-audio-blk-ctrl"; >>>> + reg = <0x30e20000 0x10000>; >>>> + #clock-cells = <1>; >>>> + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, >>>> + <&clk IMX8MP_CLK_SAI1>, >>>> + <&clk IMX8MP_CLK_SAI2>, >>>> + <&clk IMX8MP_CLK_SAI3>, >>>> + <&clk IMX8MP_CLK_SAI5>, >>>> + <&clk IMX8MP_CLK_SAI6>, >>>> + <&clk IMX8MP_CLK_SAI7>; >>>> + clock-names = "ahb", >>>> + "sai1", "sai2", "sai3", >>>> + "sai5", "sai6", "sai7"; >>>> + power-domains = <&pgc_audio>; >>>> + }; >>>> + }; >>>> + >>> >>> I am trying to plumb in the micfil driver with a PDM microphone on a >>> Plus. I have SAI3 and SAI5 audio working, but if I try to use the >>> micfil, the PDM clock doesn't get turned on, and the micfil doesn't >>> appear to see anything coming in. I was curious why the >>> audio_blk_ctrl has clock entries for IMX8MP_CLK_SAIx, but there isn't >>> one for the PDM nor the ASRC clocks. >> >> I only ever needed SAI, so that was what was tested on the EVK . > > That makes sense. > >> >>> I added the MICFIL noted to the >>> 8mp in a previous patch [1], and I am trying to customize the MICFIL >>> node as follows: >>> >>> &micfil { >>> #sound-dai-cells = <0>; >>> pinctrl-names = "default"; >>> pinctrl-0 = <&pinctrl_pdm>; >>> assigned-clocks = <&clk IMX8MP_CLK_PDM>; >>> assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; >>> assigned-clock-rates = <196608000>; >>> status = "okay"; >>> }; >>> >>> I also noticed in the down-stream kernel, the pdm_ipg_clk and >>> pdm_root_clk are shared gates with separate parents. >>> >>> The PDM tree of the down-stream kernel looks like this: >>> audio_pll1_ref_sel 0 0 0 24000000 >>> 0 0 50000 Y >>> audio_pll1 0 0 0 393216000 >>> 0 0 50000 Y >>> audio_pll1_bypass 0 0 0 393216000 >>> 0 0 50000 Y >>> audio_pll1_out 0 0 0 393216000 >>> 0 0 50000 N >>> pdm 0 0 0 196608000 >>> 0 0 50000 N >>> pdm_root 0 0 0 196608000 >>> 0 0 50000 N >>> pdm_sel 0 0 0 196608000 >>> 0 0 50000 Y >>> pdm_root_clk 0 0 0 >>> 196608000 0 0 50000 N >>> >>> The PDM tree of the mainline looks like this: >>> >>> audio_pll1_ref_sel 0 0 0 24000000 >>> 0 0 50000 Y >>> audio_pll1 0 0 0 393216000 >>> 0 0 50000 Y >>> audio_pll1_bypass 0 0 0 393216000 >>> 0 0 50000 Y >>> audio_pll1_out 0 0 0 393216000 >>> 0 0 50000 N >>> pdm 0 0 0 196608000 >>> 0 0 50000 N >>> pdm_root 0 0 0 196608000 >>> 0 0 50000 N >>> pdm_sel 0 0 0 196608000 >>> 0 0 50000 Y >>> >>> It seems like the "pdm_root_clk" generated by the shared audo-blk >>> down-sream driver is missing from the mainline. I looked up the clock >>> I referenced when I attempted to enable the miffil, but >>> 'IMX8MP_CLK_AUDIOMIX_PDM_ROOT doesn't appear to be configured in >>> either clk-imx8mp.c or clk-imx8mp-audiomix.c. Maybe it's obscured by >>> the macros, but it seems like the pdm_sel should somehow have an >>> additional variable for the shared clock and an additional clock like >>> pdm_root_clk assigned with it. >>> >>> I have similar configurations for Mini and Nano, and both of them are >>> able to record audio, so I think there might be a clock issue >>> somewhere related to the audiomix driver, and not a misconfiguration >>> of the sound-card or the micfil itself. >> >> Shouldn't the micfil be somehow a consumer of the pdm_sel clock , and >> enable those clock in the driver ? > > Micfil references IMX8MP_CLK_AUDIOMIX_PDM_IPG, and > IMX8MP_CLK_AUDIOMIX_PDM_ROOT. I am not convinced the > IMX8MP_CLK_AUDIOMIX_PDM_ROOT exists beyond a #define in an include > directory. I tried making it use pdm_sel, but it threw an error. I > am not near my system, so I'm sorry I don't have more details. > > In the downstream kernel IMX8MP_CLK_AUDIOMIX_PDM_ROOT was a child of > pdm_sel, but I am not certain as to what the difference between them > was since they appeared to be shared. The pdm_sel is definitely a mux . Is there a follow-up gate after the mux ?
On Wed, Aug 30, 2023 at 3:50 PM Marek Vasut <marex@denx.de> wrote: > > On 8/30/23 21:59, Adam Ford wrote: > > On Wed, Aug 30, 2023 at 2:10 PM Marek Vasut <marex@denx.de> wrote: > >> > >> On 8/30/23 04:44, Adam Ford wrote: > >> > >> Hi, > >> > >>> I have a question about the clocking for eASRC and PDM. > >>> > >>>> + > >>>> + audio_blk_ctrl: clock-controller@30e20000 { > >>>> + compatible = "fsl,imx8mp-audio-blk-ctrl"; > >>>> + reg = <0x30e20000 0x10000>; > >>>> + #clock-cells = <1>; > >>>> + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, > >>>> + <&clk IMX8MP_CLK_SAI1>, > >>>> + <&clk IMX8MP_CLK_SAI2>, > >>>> + <&clk IMX8MP_CLK_SAI3>, > >>>> + <&clk IMX8MP_CLK_SAI5>, > >>>> + <&clk IMX8MP_CLK_SAI6>, > >>>> + <&clk IMX8MP_CLK_SAI7>; > >>>> + clock-names = "ahb", > >>>> + "sai1", "sai2", "sai3", > >>>> + "sai5", "sai6", "sai7"; > >>>> + power-domains = <&pgc_audio>; > >>>> + }; > >>>> + }; > >>>> + > >>> > >>> I am trying to plumb in the micfil driver with a PDM microphone on a > >>> Plus. I have SAI3 and SAI5 audio working, but if I try to use the > >>> micfil, the PDM clock doesn't get turned on, and the micfil doesn't > >>> appear to see anything coming in. I was curious why the > >>> audio_blk_ctrl has clock entries for IMX8MP_CLK_SAIx, but there isn't > >>> one for the PDM nor the ASRC clocks. > >> > >> I only ever needed SAI, so that was what was tested on the EVK . > > > > That makes sense. > > > >> > >>> I added the MICFIL noted to the > >>> 8mp in a previous patch [1], and I am trying to customize the MICFIL > >>> node as follows: > >>> > >>> &micfil { > >>> #sound-dai-cells = <0>; > >>> pinctrl-names = "default"; > >>> pinctrl-0 = <&pinctrl_pdm>; > >>> assigned-clocks = <&clk IMX8MP_CLK_PDM>; > >>> assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; > >>> assigned-clock-rates = <196608000>; > >>> status = "okay"; > >>> }; > >>> > >>> I also noticed in the down-stream kernel, the pdm_ipg_clk and > >>> pdm_root_clk are shared gates with separate parents. > >>> > >>> The PDM tree of the down-stream kernel looks like this: > >>> audio_pll1_ref_sel 0 0 0 24000000 > >>> 0 0 50000 Y > >>> audio_pll1 0 0 0 393216000 > >>> 0 0 50000 Y > >>> audio_pll1_bypass 0 0 0 393216000 > >>> 0 0 50000 Y > >>> audio_pll1_out 0 0 0 393216000 > >>> 0 0 50000 N > >>> pdm 0 0 0 196608000 > >>> 0 0 50000 N > >>> pdm_root 0 0 0 196608000 > >>> 0 0 50000 N > >>> pdm_sel 0 0 0 196608000 > >>> 0 0 50000 Y > >>> pdm_root_clk 0 0 0 > >>> 196608000 0 0 50000 N > >>> > >>> The PDM tree of the mainline looks like this: > >>> > >>> audio_pll1_ref_sel 0 0 0 24000000 > >>> 0 0 50000 Y > >>> audio_pll1 0 0 0 393216000 > >>> 0 0 50000 Y > >>> audio_pll1_bypass 0 0 0 393216000 > >>> 0 0 50000 Y > >>> audio_pll1_out 0 0 0 393216000 > >>> 0 0 50000 N > >>> pdm 0 0 0 196608000 > >>> 0 0 50000 N > >>> pdm_root 0 0 0 196608000 > >>> 0 0 50000 N > >>> pdm_sel 0 0 0 196608000 > >>> 0 0 50000 Y > >>> > >>> It seems like the "pdm_root_clk" generated by the shared audo-blk > >>> down-sream driver is missing from the mainline. I looked up the clock > >>> I referenced when I attempted to enable the miffil, but > >>> 'IMX8MP_CLK_AUDIOMIX_PDM_ROOT doesn't appear to be configured in > >>> either clk-imx8mp.c or clk-imx8mp-audiomix.c. Maybe it's obscured by > >>> the macros, but it seems like the pdm_sel should somehow have an > >>> additional variable for the shared clock and an additional clock like > >>> pdm_root_clk assigned with it. > >>> > >>> I have similar configurations for Mini and Nano, and both of them are > >>> able to record audio, so I think there might be a clock issue > >>> somewhere related to the audiomix driver, and not a misconfiguration > >>> of the sound-card or the micfil itself. > >> > >> Shouldn't the micfil be somehow a consumer of the pdm_sel clock , and > >> enable those clock in the driver ? > > > > Micfil references IMX8MP_CLK_AUDIOMIX_PDM_IPG, and > > IMX8MP_CLK_AUDIOMIX_PDM_ROOT. I am not convinced the > > IMX8MP_CLK_AUDIOMIX_PDM_ROOT exists beyond a #define in an include > > directory. I tried making it use pdm_sel, but it threw an error. I > > am not near my system, so I'm sorry I don't have more details. > > > > In the downstream kernel IMX8MP_CLK_AUDIOMIX_PDM_ROOT was a child of > > pdm_sel, but I am not certain as to what the difference between them > > was since they appeared to be shared. > > The pdm_sel is definitely a mux . Is there a follow-up gate after the mux ? Not that I could see. I think I was just overthinking it. I saw the IMX8MP_CLK_AUDIOMIX_PDM_ROOT in mx8mp-clock.h which matched the reference in the downstream kernel, so I was expecting that to be the same clock name. When it didn't work, I thought I was missing something because I only saw the pdm_sel mux and no direct reason or reference to IMX8MP_CLK_AUDIOMIX_PDM_ROOT. I have it working now. Sorry for the noise. I'll get my series cleaned up and push another revision to add micfil node to the 8mp, and I'll probably remove the IMX8MP_CLK_AUDIOMIX_PDM_ROOT imx8mp-clock.h so it doesn't throw someone else off. I appreciate your input. adam
On 8/31/23 06:32, Adam Ford wrote: > On Wed, Aug 30, 2023 at 3:50 PM Marek Vasut <marex@denx.de> wrote: >> >> On 8/30/23 21:59, Adam Ford wrote: >>> On Wed, Aug 30, 2023 at 2:10 PM Marek Vasut <marex@denx.de> wrote: >>>> >>>> On 8/30/23 04:44, Adam Ford wrote: >>>> >>>> Hi, >>>> >>>>> I have a question about the clocking for eASRC and PDM. >>>>> >>>>>> + >>>>>> + audio_blk_ctrl: clock-controller@30e20000 { >>>>>> + compatible = "fsl,imx8mp-audio-blk-ctrl"; >>>>>> + reg = <0x30e20000 0x10000>; >>>>>> + #clock-cells = <1>; >>>>>> + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, >>>>>> + <&clk IMX8MP_CLK_SAI1>, >>>>>> + <&clk IMX8MP_CLK_SAI2>, >>>>>> + <&clk IMX8MP_CLK_SAI3>, >>>>>> + <&clk IMX8MP_CLK_SAI5>, >>>>>> + <&clk IMX8MP_CLK_SAI6>, >>>>>> + <&clk IMX8MP_CLK_SAI7>; >>>>>> + clock-names = "ahb", >>>>>> + "sai1", "sai2", "sai3", >>>>>> + "sai5", "sai6", "sai7"; >>>>>> + power-domains = <&pgc_audio>; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>> >>>>> I am trying to plumb in the micfil driver with a PDM microphone on a >>>>> Plus. I have SAI3 and SAI5 audio working, but if I try to use the >>>>> micfil, the PDM clock doesn't get turned on, and the micfil doesn't >>>>> appear to see anything coming in. I was curious why the >>>>> audio_blk_ctrl has clock entries for IMX8MP_CLK_SAIx, but there isn't >>>>> one for the PDM nor the ASRC clocks. >>>> >>>> I only ever needed SAI, so that was what was tested on the EVK . >>> >>> That makes sense. >>> >>>> >>>>> I added the MICFIL noted to the >>>>> 8mp in a previous patch [1], and I am trying to customize the MICFIL >>>>> node as follows: >>>>> >>>>> &micfil { >>>>> #sound-dai-cells = <0>; >>>>> pinctrl-names = "default"; >>>>> pinctrl-0 = <&pinctrl_pdm>; >>>>> assigned-clocks = <&clk IMX8MP_CLK_PDM>; >>>>> assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; >>>>> assigned-clock-rates = <196608000>; >>>>> status = "okay"; >>>>> }; >>>>> >>>>> I also noticed in the down-stream kernel, the pdm_ipg_clk and >>>>> pdm_root_clk are shared gates with separate parents. >>>>> >>>>> The PDM tree of the down-stream kernel looks like this: >>>>> audio_pll1_ref_sel 0 0 0 24000000 >>>>> 0 0 50000 Y >>>>> audio_pll1 0 0 0 393216000 >>>>> 0 0 50000 Y >>>>> audio_pll1_bypass 0 0 0 393216000 >>>>> 0 0 50000 Y >>>>> audio_pll1_out 0 0 0 393216000 >>>>> 0 0 50000 N >>>>> pdm 0 0 0 196608000 >>>>> 0 0 50000 N >>>>> pdm_root 0 0 0 196608000 >>>>> 0 0 50000 N >>>>> pdm_sel 0 0 0 196608000 >>>>> 0 0 50000 Y >>>>> pdm_root_clk 0 0 0 >>>>> 196608000 0 0 50000 N >>>>> >>>>> The PDM tree of the mainline looks like this: >>>>> >>>>> audio_pll1_ref_sel 0 0 0 24000000 >>>>> 0 0 50000 Y >>>>> audio_pll1 0 0 0 393216000 >>>>> 0 0 50000 Y >>>>> audio_pll1_bypass 0 0 0 393216000 >>>>> 0 0 50000 Y >>>>> audio_pll1_out 0 0 0 393216000 >>>>> 0 0 50000 N >>>>> pdm 0 0 0 196608000 >>>>> 0 0 50000 N >>>>> pdm_root 0 0 0 196608000 >>>>> 0 0 50000 N >>>>> pdm_sel 0 0 0 196608000 >>>>> 0 0 50000 Y >>>>> >>>>> It seems like the "pdm_root_clk" generated by the shared audo-blk >>>>> down-sream driver is missing from the mainline. I looked up the clock >>>>> I referenced when I attempted to enable the miffil, but >>>>> 'IMX8MP_CLK_AUDIOMIX_PDM_ROOT doesn't appear to be configured in >>>>> either clk-imx8mp.c or clk-imx8mp-audiomix.c. Maybe it's obscured by >>>>> the macros, but it seems like the pdm_sel should somehow have an >>>>> additional variable for the shared clock and an additional clock like >>>>> pdm_root_clk assigned with it. >>>>> >>>>> I have similar configurations for Mini and Nano, and both of them are >>>>> able to record audio, so I think there might be a clock issue >>>>> somewhere related to the audiomix driver, and not a misconfiguration >>>>> of the sound-card or the micfil itself. >>>> >>>> Shouldn't the micfil be somehow a consumer of the pdm_sel clock , and >>>> enable those clock in the driver ? >>> >>> Micfil references IMX8MP_CLK_AUDIOMIX_PDM_IPG, and >>> IMX8MP_CLK_AUDIOMIX_PDM_ROOT. I am not convinced the >>> IMX8MP_CLK_AUDIOMIX_PDM_ROOT exists beyond a #define in an include >>> directory. I tried making it use pdm_sel, but it threw an error. I >>> am not near my system, so I'm sorry I don't have more details. >>> >>> In the downstream kernel IMX8MP_CLK_AUDIOMIX_PDM_ROOT was a child of >>> pdm_sel, but I am not certain as to what the difference between them >>> was since they appeared to be shared. >> >> The pdm_sel is definitely a mux . Is there a follow-up gate after the mux ? > > Not that I could see. I think I was just overthinking it. I saw the > IMX8MP_CLK_AUDIOMIX_PDM_ROOT in mx8mp-clock.h which matched the > reference in the downstream kernel, so I was expecting that to be the > same clock name. When it didn't work, I thought I was missing > something because I only saw the pdm_sel mux and no direct reason or > reference to IMX8MP_CLK_AUDIOMIX_PDM_ROOT. I have it working now. > Sorry for the noise. I'll get my series cleaned up and push another > revision to add micfil node to the 8mp, and I'll probably remove the > IMX8MP_CLK_AUDIOMIX_PDM_ROOT imx8mp-clock.h so it doesn't throw > someone else off. No worries, good thing you found it. Thanks for investigating it.
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index f81391993354f..149f4e7e1d9b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -595,6 +595,13 @@ pgc_usb2_phy: power-domain@3 { reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; }; + pgc_audio: power-domain@5 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI>; + }; + pgc_gpu2d: power-domain@6 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_GPU2D>; @@ -1167,6 +1174,157 @@ opp-1000000000 { }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c10000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c20000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c30000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c50000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c60000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c80000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e00000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e10000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + audio_blk_ctrl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl"; + reg = <0x30e20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_SAI1>, + <&clk IMX8MP_CLK_SAI2>, + <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_CLK_SAI5>, + <&clk IMX8MP_CLK_SAI6>, + <&clk IMX8MP_CLK_SAI7>; + clock-names = "ahb", + "sai1", "sai2", "sai3", + "sai5", "sai6", "sai7"; + power-domains = <&pgc_audio>; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>;