[RFC,1/3] clk: renesas: rcar-gen3: Add support for ZG clock

Commit Message

Adam Ford May 30, 2023, 11:20 a.m. UTC

A clock used for the 3D graphics appears to be common
among multiple SoC's, so add a generic gen3 clock
for clocking the graphics.

Signed-off-by: Adam Ford <[e-mail]>

Comments

Geert Uytterhoeven June 7, 2023, 1:17 p.m. UTC | #1

Hi Adam,

On Tue, May 30, 2023 at 1:21 PM Adam Ford <[e-mail]> wrote:
> A clock used for the 3D graphics appears to be common
> among multiple SoC's, so add a generic gen3 clock
> for clocking the graphics.
>
> Signed-off-by: Adam Ford <[e-mail]>

Thanks for your patch!

> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -301,6 +301,39 @@ static struct clk * __init cpg_z_clk_register(const char *name,
>         return clk;
>  }
>
> +static struct clk * __init cpg_zg_clk_register(const char *name,
> +                                              const char *parent_name,
> +                                              void __iomem *reg,
> +                                              unsigned int div,
> +                                              unsigned int offset)
> +{
> +       struct clk_init_data init;

"= {};", as you do not initialize all fields below.

> +       struct cpg_z_clk *zclk;
> +       struct clk *clk;
> +
> +       zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
> +       if (!zclk)
> +               return ERR_PTR(-ENOMEM);
> +
> +       init.name = name;
> +       init.ops = &cpg_z_clk_ops;
> +       init.flags = 0;
> +       init.parent_names = &parent_name;
> +       init.num_parents = 1;
> +
> +       zclk->reg = reg + CPG_FRQCRB;
> +       zclk->kick_reg = reg + CPG_FRQCRB;
> +       zclk->hw.init = &init;
> +       zclk->mask = GENMASK(offset + 4, offset);
> +       zclk->fixed_div = div; /* PLLVCO x 1/div1 x 3DGE divider x 1/div2 */
> +
> +       clk = clk_register(NULL, &zclk->hw);
> +       if (IS_ERR(clk))
> +               kfree(zclk);
> +
> +       return clk;
> +}

This new function is very similar to the existing cpg_z_clk_register().
The only differences are:
  - init.flags = 0 vs. CLK_SET_RATE_PARENT, which should not matter
    much,
  - register CPG_FRQCRB vs. CPG_FRQCRC.

So I think it would be good to avoid duplication by adding a register
parameter to cpg_z_clk_register(), to pass the Frequency Control Register
offset to use.


> +
>  static const struct clk_div_table cpg_rpcsrc_div_table[] = {
>         { 2, 5 }, { 3, 6 }, { 0, 0 },
>  };
> @@ -502,6 +535,9 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
>         case CLK_TYPE_GEN3_RPCD2:
>                 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
>                                               __clk_get_name(parent));
> +       case CLK_TYPE_GEN3_ZG:
> +               return cpg_zg_clk_register(core->name, __clk_get_name(parent),
> +                                          base, core->div, core->offset);

Please insert this right below the CLK_TYPE_GEN3_Z case.

>         default:
>                 return ERR_PTR(-EINVAL);

The rest LGTM.

(Ideally, we wouldn't need a new clock type, and could just use
 CLK_TYPE_GEN3_Z.  But then we would need to add a new field to struct
 cpg_core_clk to store the FRQCR offset, as the .offset field is already
 in use, which would increase all clock table sizes a lot.  Or we can
 encode both register and bit offset in .offset...
 All of this needs a big overhaul for switching to of_clk_add_hw_provider()
 anyway, so I wouldn't bother for now.)

Gr{oetje,eeting}s,

                        Geert

Patch

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index b3ef62fa612e..7abfbf77a497 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -301,6 +301,39 @@  static struct clk * __init cpg_z_clk_register(const char *name,
 	return clk;
 }
 
+static struct clk * __init cpg_zg_clk_register(const char *name,
+					       const char *parent_name,
+					       void __iomem *reg,
+					       unsigned int div,
+					       unsigned int offset)
+{
+	struct clk_init_data init;
+	struct cpg_z_clk *zclk;
+	struct clk *clk;
+
+	zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
+	if (!zclk)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &cpg_z_clk_ops;
+	init.flags = 0;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	zclk->reg = reg + CPG_FRQCRB;
+	zclk->kick_reg = reg + CPG_FRQCRB;
+	zclk->hw.init = &init;
+	zclk->mask = GENMASK(offset + 4, offset);
+	zclk->fixed_div = div; /* PLLVCO x 1/div1 x 3DGE divider x 1/div2 */
+
+	clk = clk_register(NULL, &zclk->hw);
+	if (IS_ERR(clk))
+		kfree(zclk);
+
+	return clk;
+}
+
 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
 	{ 2, 5 }, { 3, 6 }, { 0, 0 },
 };
@@ -502,6 +535,9 @@  struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 	case CLK_TYPE_GEN3_RPCD2:
 		return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
 					      __clk_get_name(parent));
+	case CLK_TYPE_GEN3_ZG:
+		return cpg_zg_clk_register(core->name, __clk_get_name(parent),
+					   base, core->div, core->offset);
 
 	default:
 		return ERR_PTR(-EINVAL);
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 9028bf4295ce..bfdc649bdf12 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -22,6 +22,7 @@  enum rcar_gen3_clk_types {
 	CLK_TYPE_GEN3_R,
 	CLK_TYPE_GEN3_MDSEL,	/* Select parent/divider using mode pin */
 	CLK_TYPE_GEN3_Z,
+	CLK_TYPE_GEN3_ZG,
 	CLK_TYPE_GEN3_OSC,	/* OSC EXTAL predivider and fixed divider */
 	CLK_TYPE_GEN3_RCKSEL,	/* Select parent/divider using RCKCR.CKSEL */
 	CLK_TYPE_GEN3_RPCSRC,