| Message ID | 20230822082750.27633-2-yu.tu@amlogic.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add S4 SoC PLLs and Peripheral clock | expand |
On 22/08/2023 10:27, Yu Tu wrote: > Add the S4 PLL clock controller dt-bindings in the S4 SoC family. > > Signed-off-by: Yu Tu <yu.tu@amlogic.com> Lovely. I sent youa friendly reminder at v8 which turns our you ignored. You keep ignoring, I will start ignoring as well from now on. Best regards, Krzysztof
On 2023/8/23 0:32, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 22/08/2023 10:27, Yu Tu wrote: >> Add the S4 PLL clock controller dt-bindings in the S4 SoC family. >> >> Signed-off-by: Yu Tu <yu.tu@amlogic.com> > > Lovely. I sent youa friendly reminder at v8 which turns our you > ignored. You keep ignoring, I will start ignoring as well from now on. Hi Krzysztof， Sorry. I did not forget the friendly reminder in v8, I consulted you for this at the time, so I re-sent V9 after adding the tag. Because it was just "meson" that was removed. But V10 is based on Neil's patch, which I think is a bit of a change. So I didn't dare add it. Instead of forgetting your reminder. So what should I do, I'll follow your advice exactly. > > Best regards, > Krzysztof >
On 23/08/2023 04:24, Yu Tu wrote: > > > On 2023/8/23 0:32, Krzysztof Kozlowski wrote: >> [ EXTERNAL EMAIL ] >>> On 22/08/2023 10:27, Yu Tu wrote: >>> Add the S4 PLL clock controller dt-bindings in the S4 SoC family. >>> >>> Signed-off-by: Yu Tu <yu.tu@amlogic.com> >> >> Lovely. I sent youa friendly reminder at v8 which turns our you >> ignored. You keep ignoring, I will start ignoring as well from now on. > > Hi Krzysztof， > > Sorry. I did not forget the friendly reminder in v8, I consulted you for > this at the time, so I re-sent V9 after adding the tag. Because it was > just "meson" that was removed. But V10 is based on Neil's patch, which I > think is a bit of a change. So I didn't dare add it. Instead of > forgetting your reminder. > > So what should I do, I'll follow your advice exactly. I don't think there was much difference between the version, which received the review, and the current patch. Otherwise your changelog should say that you drop Rb tag. Rebasing of something somewhere is not the reason, so please describe what are the differences in the patch? Best regards, Krzysztof
On 2023/8/23 13:43, Krzysztof Kozlowski wrote: > > [ EXTERNAL EMAIL ] > > On 23/08/2023 04:24, Yu Tu wrote: >> >> >> On 2023/8/23 0:32, Krzysztof Kozlowski wrote: >>> [ EXTERNAL EMAIL ] >>>> On 22/08/2023 10:27, Yu Tu wrote: >>>> Add the S4 PLL clock controller dt-bindings in the S4 SoC family. >>>> >>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com> >>> >>> Lovely. I sent youa friendly reminder at v8 which turns our you >>> ignored. You keep ignoring, I will start ignoring as well from now on. >> >> Hi Krzysztof， >> >> Sorry. I did not forget the friendly reminder in v8, I consulted you for >> this at the time, so I re-sent V9 after adding the tag. Because it was >> just "meson" that was removed. But V10 is based on Neil's patch, which I >> think is a bit of a change. So I didn't dare add it. Instead of >> forgetting your reminder. >> >> So what should I do, I'll follow your advice exactly. > > I don't think there was much difference between the version, which > received the review, and the current patch. Otherwise your changelog > should say that you drop Rb tag. Rebasing of something somewhere is not > the reason, so please describe what are the differences in the patch? The current patch and V9 patch difference is mainly based on Neil patch I put "include/dt - bindings/clock/amlogic,s4-pll-clkc.h" this document describes the clock index all exposed. Next, I should add Rob's tag and resend it. If you have any other suggestions, please tell me and I will strictly follow your suggestions. > > Best regards, > Krzysztof >
On 23/08/2023 08:20, Yu Tu wrote: > > > On 2023/8/23 13:43, Krzysztof Kozlowski wrote: >> >> [ EXTERNAL EMAIL ] >> >> On 23/08/2023 04:24, Yu Tu wrote: >>> >>> >>> On 2023/8/23 0:32, Krzysztof Kozlowski wrote: >>>> [ EXTERNAL EMAIL ] >>>>> On 22/08/2023 10:27, Yu Tu wrote: >>>>> Add the S4 PLL clock controller dt-bindings in the S4 SoC family. >>>>> >>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com> >>>> >>>> Lovely. I sent youa friendly reminder at v8 which turns our you >>>> ignored. You keep ignoring, I will start ignoring as well from now on. >>> >>> Hi Krzysztof， >>> >>> Sorry. I did not forget the friendly reminder in v8, I consulted you for >>> this at the time, so I re-sent V9 after adding the tag. Because it was >>> just "meson" that was removed. But V10 is based on Neil's patch, which I >>> think is a bit of a change. So I didn't dare add it. Instead of >>> forgetting your reminder. >>> >>> So what should I do, I'll follow your advice exactly. >> >> I don't think there was much difference between the version, which >> received the review, and the current patch. Otherwise your changelog >> should say that you drop Rb tag. Rebasing of something somewhere is not >> the reason, so please describe what are the differences in the patch? > > The current patch and V9 patch difference is mainly based on Neil patch > I put "include/dt - bindings/clock/amlogic,s4-pll-clkc.h" this document > describes the clock index all exposed. Adding one include is insignificant change, thus any Rb tags should stay. > > Next, I should add Rob's tag and resend it. If you have any other > suggestions, please tell me and I will strictly follow your suggestions. I cannot add someone's tag, thus on your next version you must include it. I told this last time. Best regards, Krzysztof
On 2023/8/23 14:27, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 23/08/2023 08:20, Yu Tu wrote: >> >> >> On 2023/8/23 13:43, Krzysztof Kozlowski wrote: >>> >>> [ EXTERNAL EMAIL ] >>> >>> On 23/08/2023 04:24, Yu Tu wrote: >>>> >>>> >>>> On 2023/8/23 0:32, Krzysztof Kozlowski wrote: >>>>> [ EXTERNAL EMAIL ] >>>>>> On 22/08/2023 10:27, Yu Tu wrote: >>>>>> Add the S4 PLL clock controller dt-bindings in the S4 SoC family. >>>>>> >>>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com> >>>>> >>>>> Lovely. I sent youa friendly reminder at v8 which turns our you >>>>> ignored. You keep ignoring, I will start ignoring as well from now on. >>>> >>>> Hi Krzysztof， >>>> >>>> Sorry. I did not forget the friendly reminder in v8, I consulted you for >>>> this at the time, so I re-sent V9 after adding the tag. Because it was >>>> just "meson" that was removed. But V10 is based on Neil's patch, which I >>>> think is a bit of a change. So I didn't dare add it. Instead of >>>> forgetting your reminder. >>>> >>>> So what should I do, I'll follow your advice exactly. >>> >>> I don't think there was much difference between the version, which >>> received the review, and the current patch. Otherwise your changelog >>> should say that you drop Rb tag. Rebasing of something somewhere is not >>> the reason, so please describe what are the differences in the patch? >> >> The current patch and V9 patch difference is mainly based on Neil patch >> I put "include/dt - bindings/clock/amlogic,s4-pll-clkc.h" this document >> describes the clock index all exposed. > > Adding one include is insignificant change, thus any Rb tags should stay. I got it. >> >> Next, I should add Rob's tag and resend it. If you have any other >> suggestions, please tell me and I will strictly follow your suggestions. > > I cannot add someone's tag, thus on your next version you must include > it. I told this last time. Well. I remember your advice. Guaranteed no errors in the next version. > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml new file mode 100644 index 000000000000..d8932ec26ca8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic S4 PLL Clock Controller + +maintainers: + - Yu Tu <yu.tu@amlogic.com> + +properties: + compatible: + const: amlogic,s4-pll-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clkc_pll: clock-controller@fe008000 { + compatible = "amlogic,s4-pll-clkc"; + reg = <0xfe008000 0x1e8>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/amlogic,s4-pll-clkc.h b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h new file mode 100644 index 000000000000..af9f110f8b62 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved. + * Author: Yu Tu <yu.tu@amlogic.com> + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H + +#define CLKID_FIXED_PLL_DCO 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2_DIV 2 +#define CLKID_FCLK_DIV2 3 +#define CLKID_FCLK_DIV3_DIV 4 +#define CLKID_FCLK_DIV3 5 +#define CLKID_FCLK_DIV4_DIV 6 +#define CLKID_FCLK_DIV4 7 +#define CLKID_FCLK_DIV5_DIV 8 +#define CLKID_FCLK_DIV5 9 +#define CLKID_FCLK_DIV7_DIV 10 +#define CLKID_FCLK_DIV7 11 +#define CLKID_FCLK_DIV2P5_DIV 12 +#define CLKID_FCLK_DIV2P5 13 +#define CLKID_GP0_PLL_DCO 14 +#define CLKID_GP0_PLL 15 +#define CLKID_HIFI_PLL_DCO 16 +#define CLKID_HIFI_PLL 17 +#define CLKID_HDMI_PLL_DCO 18 +#define CLKID_HDMI_PLL_OD 19 +#define CLKID_HDMI_PLL 20 +#define CLKID_MPLL_50M_DIV 21 +#define CLKID_MPLL_50M 22 +#define CLKID_MPLL_PREDIV 23 +#define CLKID_MPLL0_DIV 24 +#define CLKID_MPLL0 25 +#define CLKID_MPLL1_DIV 26 +#define CLKID_MPLL1 27 +#define CLKID_MPLL2_DIV 28 +#define CLKID_MPLL2 29 +#define CLKID_MPLL3_DIV 30 +#define CLKID_MPLL3 31 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */
Add the S4 PLL clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> --- .../bindings/clock/amlogic,s4-pll-clkc.yaml | 49 +++++++++++++++++++ .../dt-bindings/clock/amlogic,s4-pll-clkc.h | 43 ++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h