diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
deleted file mode 100644
index 3a8948c04bc9..000000000000
--- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* Amlogic AXG Audio Clock Controllers
-
-The Amlogic AXG audio clock controller generates and supplies clock to the
-other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
-devices.
-
-Required Properties:
-
-- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,
-		  "amlogic,g12a-audio-clkc" for G12A,
-		  "amlogic,sm1-audio-clkc" for S905X3.
-- reg		: physical base address of the clock controller and length of
-		  memory mapped region.
-- clocks	: a list of phandle + clock-specifier pairs for the clocks listed
-		  in clock-names.
-- clock-names	: must contain the following:
-		  * "pclk" - Main peripheral bus clock
-		  may contain the following:
-		  * "mst_in[0-7]" - 8 input plls to generate clock signals
-		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
-				      components.
-		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
-				       components.
-- resets	: phandle of the internal reset line
-- #clock-cells	: should be 1.
-- #reset-cells  : should be 1 on the g12a (and following) soc family
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
-used in device tree sources.
-
-Example:
-
-clkc_audio: clock-controller@0 {
-	compatible = "amlogic,axg-audio-clkc";
-	reg = <0x0 0x0 0x0 0xb4>;
-	#clock-cells = <1>;
-
-	clocks = <&clkc CLKID_AUDIO>,
-		 <&clkc CLKID_MPLL0>,
-		 <&clkc CLKID_MPLL1>,
-		 <&clkc CLKID_MPLL2>,
-		 <&clkc CLKID_MPLL3>,
-		 <&clkc CLKID_HIFI_PLL>,
-		 <&clkc CLKID_FCLK_DIV3>,
-		 <&clkc CLKID_FCLK_DIV4>,
-		 <&clkc CLKID_GP0_PLL>;
-	clock-names = "pclk",
-		      "mst_in0",
-		      "mst_in1",
-		      "mst_in2",
-		      "mst_in3",
-		      "mst_in4",
-		      "mst_in5",
-		      "mst_in6",
-		      "mst_in7";
-	resets = <&reset RESET_AUDIO>;
-};
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
new file mode 100644
index 000000000000..5ae2ff4efe11
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
@@ -0,0 +1,917 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic AXG Audio Clock Controller
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+  - Jerome Brunet <jbrunet@baylibre.com>
+
+description:
+  The Amlogic AXG audio clock controller generates and supplies clock to the
+  other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
+  devices.
+
+properties:
+  compatible:
+    enum:
+      - amlogic,axg-audio-clkc
+      - amlogic,g12a-audio-clkc
+      - amlogic,sm1-audio-clkc
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 29
+
+  # All clocks except pclk are optional inputs of the controller
+  # which may or may not be wired in depending on SoC variants, boards config, etc ...
+  # The order in which those clocks appear is unpredictable and does not matter.
+  # Lacking a better way to describe this, the optional clocks are repeated 28 times.
+  clock-names:
+    minItems: 1
+    items:
+      - const: pclk
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+      - enum:
+          - mst_in0
+          - mst_in1
+          - mst_in2
+          - mst_in3
+          - mst_in4
+          - mst_in5
+          - mst_in6
+          - mst_in7
+          - slv_sclk0
+          - slv_sclk1
+          - slv_sclk2
+          - slv_sclk3
+          - slv_sclk4
+          - slv_sclk5
+          - slv_sclk6
+          - slv_sclk7
+          - slv_sclk8
+          - slv_sclk9
+          - slv_lrclk0
+          - slv_lrclk1
+          - slv_lrclk2
+          - slv_lrclk3
+          - slv_lrclk4
+          - slv_lrclk5
+          - slv_lrclk6
+          - slv_lrclk7
+          - slv_lrclk8
+          - slv_lrclk9
+
+  resets:
+    description: internal reset line
+
+required:
+  - compatible
+  - '#clock-cells'
+  - reg
+  - clocks
+  - clock-names
+  - resets
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - amlogic,g12a-audio-clkc
+              - amlogic,sm1-audio-clkc
+    then:
+      required:
+        - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/axg-clkc.h>
+    #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+    apb {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clkc_audio: clock-controller@0 {
+        compatible = "amlogic,axg-audio-clkc";
+        reg = <0x0 0x0 0x0 0xb4>;
+        #clock-cells = <1>;
+
+        clocks = <&clkc CLKID_AUDIO>,
+            <&clkc CLKID_MPLL0>,
+            <&clkc CLKID_MPLL1>,
+            <&clkc CLKID_MPLL2>,
+            <&clkc CLKID_HIFI_PLL>,
+            <&clkc CLKID_FCLK_DIV3>,
+            <&clkc CLKID_FCLK_DIV4>,
+            <&clkc CLKID_GP0_PLL>,
+            <&codec_frame_clk>;
+        clock-names = "pclk",
+            "mst_in0",
+            "mst_in1",
+            "mst_in2",
+            "mst_in4",
+            "mst_in5",
+            "mst_in6",
+            "mst_in7",
+            "slv_lrclk1";
+        resets = <&reset RESET_AUDIO>;
+      };
+    };
